^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DW_HDMI__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DW_HDMI__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <drm/drm_property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/hdmi-codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/cec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct drm_display_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct drm_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct drm_encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct dw_hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct dw_hdmi_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * DOC: Supported input formats and encodings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Depending on the Hardware configuration of the Controller IP, it supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * a subset of the following input formats and encodings on its internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 48bit bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * | Format Name | Format Code | Encodings |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * | | | or ``V4L2_YCBCR_ENC_XV601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * | | | or ``V4L2_YCBCR_ENC_XV709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * | | | or ``V4L2_YCBCR_ENC_XV601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * | | | or ``V4L2_YCBCR_ENC_XV709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * | | | or ``V4L2_YCBCR_ENC_XV601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * | | | or ``V4L2_YCBCR_ENC_XV709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * | | | or ``V4L2_YCBCR_ENC_XV601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * | | | or ``V4L2_YCBCR_ENC_XV709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * | | | or ``V4L2_YCBCR_ENC_709`` |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * +----------------------+----------------------------------+------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SUPPORT_HDMI_ALLM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DW_HDMI_RES_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DW_HDMI_RES_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DW_HDMI_RES_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DW_HDMI_RES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum dw_hdmi_phy_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DW_HDMI_PHY_VENDOR_PHY = 0xfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct dw_hdmi_audio_frl_n {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int r_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int n_32k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int n_44k1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int n_48k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct dw_hdmi_audio_tmds_n {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long tmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int n_32k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int n_44k1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int n_48k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct dw_hdmi_mpll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long mpixelclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 cpce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 gmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } res[DW_HDMI_RES_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct dw_hdmi_curr_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long mpixelclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u16 curr[DW_HDMI_RES_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct dw_hdmi_phy_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long mpixelclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 sym_ctr; /*clock symbol and transmitter control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 term; /*transmission termination value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 vlev_ctr; /* voltage level control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct dw_hdmi_link_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool dsc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool frl_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int frl_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int rate_per_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int hcactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 add_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 pps_payload[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct dw_hdmi_phy_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int (*init)(struct dw_hdmi *hdmi, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const struct drm_display_info *display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void (*disable)(struct dw_hdmi *hdmi, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void (*update_hpd)(struct dw_hdmi *hdmi, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool force, bool disabled, bool rxsense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void (*setup_hpd)(struct dw_hdmi *hdmi, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct dw_hdmi_qp_phy_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int (*init)(struct dw_hdmi_qp *hdmi, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void (*disable)(struct dw_hdmi_qp *hdmi, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void (*update_hpd)(struct dw_hdmi_qp *hdmi, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool force, bool disabled, bool rxsense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void (*set_mode)(struct dw_hdmi_qp *dw_hdmi, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 mode_mask, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct dw_hdmi_property_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void (*attach_properties)(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int color, int version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void *data, bool allm_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void (*destroy_properties)(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int (*set_property)(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct drm_connector_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct drm_property *property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u64 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int (*get_property)(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const struct drm_connector_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct drm_property *property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u64 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct dw_hdmi_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct regmap *regm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long input_bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long input_bus_encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int max_tmdsclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool use_drm_infoframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool ycbcr_420_allowed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool unsupported_yuv_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool unsupported_deep_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bool is_hdmi_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Private data passed to all the .mode_valid() and .configure_phy()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * callback functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void *priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Platform-specific mode validation (optional). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Vendor PHY support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const struct dw_hdmi_phy_ops *phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const struct dw_hdmi_qp_phy_ops *qp_phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const char *phy_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void *phy_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int phy_force_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const struct dw_hdmi_audio_tmds_n *tmds_n_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* split mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bool split_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bool first_screen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct dw_hdmi_qp *left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct dw_hdmi_qp *right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Synopsys PHY support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const struct dw_hdmi_mpll_config *mpll_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const struct dw_hdmi_mpll_config *mpll_cfg_420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) const struct dw_hdmi_curr_ctrl *cur_ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) const struct dw_hdmi_phy_config *phy_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long mpixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long (*get_input_bus_format)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long (*get_output_bus_format)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long (*get_enc_in_encoding)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long (*get_enc_out_encoding)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long (*get_quant_range)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct drm_property *(*get_hdr_property)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct drm_property_blob *(*get_hdr_blob)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) bool (*get_color_changed)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int (*get_yuv422_format)(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int (*get_edid_dsc_info)(void *data, struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int (*get_next_hdr_data)(void *data, struct edid *edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct drm_connector *connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct dw_hdmi_link_config *(*get_link_cfg)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void (*set_grf_cfg)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u64 (*get_grf_color_fmt)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void (*convert_to_split_mode)(struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void (*convert_to_origin_mode)(struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int (*dclk_set)(void *data, bool enable, int vp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int (*link_clk_set)(void *data, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int (*get_vp_id)(struct drm_crtc_state *crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Vendor Property support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const struct dw_hdmi_property_ops *property_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct drm_connector *connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) const struct dw_hdmi_plat_data *plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void dw_hdmi_remove(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void dw_hdmi_unbind(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct dw_hdmi_plat_data *plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void dw_hdmi_suspend(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void dw_hdmi_resume(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct device *codec_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct drm_display_info *display);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* PHY configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned char addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bool force, bool disabled, bool rxsense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void dw_hdmi_set_cec_adap(struct dw_hdmi *hdmi, struct cec_adapter *adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void dw_hdmi_qp_set_allm_enable(struct dw_hdmi_qp *hdmi_qp, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct dw_hdmi_plat_data *plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp *hdmi, bool plug_in, bool change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp *hdmi, struct cec_adapter *adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int dw_hdmi_qp_set_earc(struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp *hdmi, unsigned int cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi, u8 *channel_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bool ref2stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp *hdmi, unsigned int ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void dw_hdmi_qp_set_audio_infoframe(struct dw_hdmi_qp *hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct hdmi_codec_params *hparms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void dw_hdmi_qp_audio_enable(struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void dw_hdmi_qp_audio_disable(struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp *hdmi, hdmi_codec_plugged_cb fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device *codec_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void dw_hdmi_qp_set_output_type(struct dw_hdmi_qp *hdmi, u64 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bool dw_hdmi_qp_get_output_whether_hdmi(struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int dw_hdmi_qp_get_output_type_cap(struct dw_hdmi_qp *hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif /* __IMX_HDMI_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags