Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * OMAP Dual-Mode Timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Thara Gopinath <thara@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Platform device conversion and hwmod support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * PWM and clock framwork support by Timo Teras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifndef __CLOCKSOURCE_DMTIMER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define __CLOCKSOURCE_DMTIMER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OMAP_TIMER_SRC_SYS_CLK			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OMAP_TIMER_SRC_32_KHZ			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define OMAP_TIMER_SRC_EXT_CLK			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* timer interrupt enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OMAP_TIMER_INT_CAPTURE			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OMAP_TIMER_INT_OVERFLOW			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OMAP_TIMER_INT_MATCH			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* trigger types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OMAP_TIMER_TRIGGER_NONE			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OMAP_TIMER_TRIGGER_OVERFLOW		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* posted mode types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OMAP_TIMER_NONPOSTED			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define OMAP_TIMER_POSTED			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* timer capabilities used in hwmod database */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define OMAP_TIMER_SECURE				0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OMAP_TIMER_ALWON				0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OMAP_TIMER_HAS_PWM				0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define OMAP_TIMER_NEEDS_RESET				0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OMAP_TIMER_HAS_DSP_IRQ				0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * timer errata flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * errata prevents us from using posted mode on these devices, unless the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * timer counter register is never read. For more details please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * the OMAP3/4/5 errata documents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OMAP_TIMER_ERRATA_I103_I767			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) struct timer_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 ocp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 tidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 tier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 twer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 tclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 tcrr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 tldr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 ttrg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 twps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 tmar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 tcar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 tsicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 tcar2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 tpir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 tnir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 tcvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 tocr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 towr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) struct omap_dm_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct clk *fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	void __iomem	*io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	void __iomem	*irq_stat;	/* TISR/IRQSTATUS interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	void __iomem	*irq_ena;	/* irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	void __iomem	*irq_dis;	/* irq disable, only on v2 ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	void __iomem	*pend;		/* write pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	void __iomem	*func_base;	/* function register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	atomic_t enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned posted:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct timer_regs context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u32 capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int omap_dm_timer_reserve_systimer(int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int omap_dm_timer_trigger(struct omap_dm_timer *timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int omap_dm_timers_active(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * Do not use the defines below, they are not needed. They should be only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * used by dmtimer.c and sys_timer related code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * The interrupt registers are different between v1 and v2 ip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * These registers are offsets from timer->iobase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP_TIMER_ID_OFFSET		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP_TIMER_OCP_CFG_OFFSET	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP_TIMER_V1_SYS_STAT_OFFSET	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP_TIMER_V1_STAT_OFFSET	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP_TIMER_V1_INT_EN_OFFSET	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP_TIMER_V2_IRQSTATUS_RAW	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP_TIMER_V2_IRQSTATUS		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP_TIMER_V2_IRQENABLE_SET	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP_TIMER_V2_IRQENABLE_CLR	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * The functional registers have a different base on v1 and v2 ip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * These registers are offsets from timer->func_base. The func_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP_TIMER_V2_FUNC_OFFSET		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define _OMAP_TIMER_WAKEUP_EN_OFFSET	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define _OMAP_TIMER_CTRL_OFFSET		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define		OMAP_TIMER_CTRL_GPOCFG		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define		OMAP_TIMER_CTRL_CAPTMODE	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define		OMAP_TIMER_CTRL_PT		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define		OMAP_TIMER_CTRL_TCM_LOWTOHIGH	(0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define		OMAP_TIMER_CTRL_TCM_HIGHTOLOW	(0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define		OMAP_TIMER_CTRL_TCM_BOTHEDGES	(0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define		OMAP_TIMER_CTRL_SCPWM		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define		OMAP_TIMER_CTRL_CE		(1 << 6) /* compare enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define		OMAP_TIMER_CTRL_PRE		(1 << 5) /* prescaler enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define		OMAP_TIMER_CTRL_PTV_SHIFT	2 /* prescaler value shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define		OMAP_TIMER_CTRL_POSTED		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define		OMAP_TIMER_CTRL_AR		(1 << 1) /* auto-reload enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define		OMAP_TIMER_CTRL_ST		(1 << 0) /* start timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define _OMAP_TIMER_COUNTER_OFFSET	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define _OMAP_TIMER_LOAD_OFFSET		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define _OMAP_TIMER_TRIGGER_OFFSET	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define _OMAP_TIMER_WRITE_PEND_OFFSET	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define		WP_NONE			0	/* no write pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define		WP_TCLR			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define		WP_TCRR			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define		WP_TLDR			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define		WP_TTGR			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define		WP_TMAR			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define		WP_TPIR			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define		WP_TNIR			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define		WP_TCVR			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define		WP_TOCR			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define		WP_TOWR			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define _OMAP_TIMER_MATCH_OFFSET	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define _OMAP_TIMER_CAPTURE_OFFSET	0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define _OMAP_TIMER_IF_CTRL_OFFSET	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define _OMAP_TIMER_CAPTURE2_OFFSET		0x44	/* TCAR2, 34xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define _OMAP_TIMER_TICK_POS_OFFSET		0x48	/* TPIR, 34xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define _OMAP_TIMER_TICK_NEG_OFFSET		0x4c	/* TNIR, 34xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define _OMAP_TIMER_TICK_COUNT_OFFSET		0x50	/* TCVR, 34xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET	0x54	/* TOCR, 34xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET	0x58	/* TOWR, 34xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* register offsets with the write pending bit encoded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define	WPSHIFT					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP_TIMER_WAKEUP_EN_REG		(_OMAP_TIMER_WAKEUP_EN_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 							| (WP_NONE << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OMAP_TIMER_CTRL_REG			(_OMAP_TIMER_CTRL_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 							| (WP_TCLR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP_TIMER_COUNTER_REG			(_OMAP_TIMER_COUNTER_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 							| (WP_TCRR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP_TIMER_LOAD_REG			(_OMAP_TIMER_LOAD_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 							| (WP_TLDR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP_TIMER_TRIGGER_REG			(_OMAP_TIMER_TRIGGER_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 							| (WP_TTGR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP_TIMER_WRITE_PEND_REG		(_OMAP_TIMER_WRITE_PEND_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 							| (WP_NONE << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OMAP_TIMER_MATCH_REG			(_OMAP_TIMER_MATCH_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 							| (WP_TMAR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP_TIMER_CAPTURE_REG			(_OMAP_TIMER_CAPTURE_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 							| (WP_NONE << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP_TIMER_IF_CTRL_REG			(_OMAP_TIMER_IF_CTRL_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 							| (WP_NONE << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OMAP_TIMER_CAPTURE2_REG			(_OMAP_TIMER_CAPTURE2_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 							| (WP_NONE << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OMAP_TIMER_TICK_POS_REG			(_OMAP_TIMER_TICK_POS_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 							| (WP_TPIR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OMAP_TIMER_TICK_NEG_REG			(_OMAP_TIMER_TICK_NEG_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 							| (WP_TNIR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OMAP_TIMER_TICK_COUNT_REG		(_OMAP_TIMER_TICK_COUNT_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 							| (WP_TCVR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OMAP_TIMER_TICK_INT_MASK_SET_REG				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * The below are inlined to optimize code size for system timers. Other code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * should not need these at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 						int posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return readl_relaxed(timer->func_base + (reg & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 					u32 reg, u32 val, int posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	writel_relaxed(val, timer->func_base + (reg & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	u32 tidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Assume v1 ip if bits [31:16] are zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	tidr = readl_relaxed(timer->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (!(tidr >> 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		timer->revision = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		timer->func_base = timer->io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		timer->revision = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		timer->pend = timer->io_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			_OMAP_TIMER_WRITE_PEND_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				OMAP_TIMER_V2_FUNC_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  * __omap_dm_timer_enable_posted - enables write posted mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * @timer:      pointer to timer instance handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * Enables the write posted mode for the timer. When posted mode is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  * writes to certain timer registers are immediately acknowledged by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  * internal bus and hence prevents stalling the CPU waiting for the write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  * complete. Enabling this feature can improve performance for writing to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * timer registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (timer->posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		timer->posted = OMAP_TIMER_NONPOSTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			      OMAP_TIMER_CTRL_POSTED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	timer->posted = OMAP_TIMER_POSTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  * __omap_dm_timer_override_errata - override errata flags for a timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  * @timer:      pointer to timer handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)  * @errata:	errata flags to be ignored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)  * For a given timer, override a timer errata by clearing the flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  * specified by the errata argument. A specific erratum should only be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  * overridden for a timer if the timer is used in such a way the erratum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  * has no impact.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 						   u32 errata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	timer->errata &= ~errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 					int posted, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (l & OMAP_TIMER_CTRL_ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		l &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #ifdef CONFIG_ARCH_OMAP2PLUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		/* Readback to make sure write has completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		 * Wait for functional clock period x 3.5 to make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		 * timer is stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		udelay(3500000 / rate + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	/* Ack possibly pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 						u32 ctrl, unsigned int load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 						int posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	__omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 						unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	writel_relaxed(value, timer->irq_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 						unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	writel_relaxed(value, timer->irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #endif /* CONFIG_ARCH_OMAP1 || CONFIG_ARCH_OMAP2PLUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif /* __CLOCKSOURCE_DMTIMER_H */