Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * TI DaVinci clocksource driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2019 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __TIMER_DAVINCI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __TIMER_DAVINCI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	DAVINCI_TIMER_CLOCKEVENT_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	DAVINCI_TIMER_CLOCKSOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	DAVINCI_TIMER_NUM_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * struct davinci_timer_cfg - davinci clocksource driver configuration struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * @reg:        register range resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * @irq:        clockevent and clocksource interrupt resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * @cmp_off:    if set - it specifies the compare register used for clockevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * Note: if the compare register is specified, the driver will use the bottom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * clock half for both clocksource and clockevent and the compare register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * to generate event irqs. The user must supply the correct compare register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * interrupt number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * This is only used by da830 the DSP of which uses the top half. The timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * driver still configures the top half to run in free-run mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct davinci_timer_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	struct resource reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	struct resource irq[DAVINCI_TIMER_NUM_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	unsigned int cmp_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int __init davinci_timer_register(struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				  const struct davinci_timer_cfg *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif /* __TIMER_DAVINCI_H__ */