^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __CLKSOURCE_ARM_ARCH_TIMER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __CLKSOURCE_ARM_ARCH_TIMER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/timecounter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ARCH_TIMER_TYPE_CP15 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ARCH_TIMER_TYPE_MEM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CNTHCTL_EL1PCTEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CNTHCTL_EL1PCEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CNTHCTL_EVNTEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CNTHCTL_EVNTDIR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CNTHCTL_EVNTI (0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum arch_timer_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ARCH_TIMER_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ARCH_TIMER_REG_TVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum arch_timer_ppi_nr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ARCH_TIMER_PHYS_SECURE_PPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ARCH_TIMER_PHYS_NONSECURE_PPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ARCH_TIMER_VIRT_PPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ARCH_TIMER_HYP_PPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ARCH_TIMER_MAX_TIMER_PPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum arch_timer_spi_nr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ARCH_TIMER_PHYS_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ARCH_TIMER_VIRT_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ARCH_TIMER_MAX_TIMER_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ARCH_TIMER_PHYS_ACCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ARCH_TIMER_VIRT_ACCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ARCH_TIMER_MEM_PHYS_ACCESS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ARCH_TIMER_MEM_VIRT_ACCESS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ARCH_TIMER_MEM_MAX_FRAMES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ARCH_TIMER_VIRT_EVT_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ARCH_TIMER_EVT_TRIGGER_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ARCH_TIMER_EVT_STREAM_PERIOD_US 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ARCH_TIMER_EVT_STREAM_FREQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct arch_timer_kvm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct timecounter timecounter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int virtual_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int physical_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct arch_timer_mem_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) phys_addr_t cntbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int phys_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int virt_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct arch_timer_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) phys_addr_t cntctlbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef CONFIG_ARM_ARCH_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern u32 arch_timer_get_rate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern u64 (*arch_timer_read_counter)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern bool arch_timer_evtstrm_available(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline u32 arch_timer_get_rate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline u64 arch_timer_read_counter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline bool arch_timer_evtstrm_available(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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