^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * watchdog driver for ZTE's zx2967 family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 ZTE Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Baoyou Xie <baoyou.xie@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ZX2967_WDT_CFG_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ZX2967_WDT_LOAD_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ZX2967_WDT_REFRESH_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ZX2967_WDT_START_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZX2967_WDT_REFRESH_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZX2967_WDT_CFG_DIV(n) ((((n) & 0xff) - 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZX2967_WDT_START_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Hardware magic number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * When watchdog reg is written, the lowest 16 bits are valid, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * the highest 16 bits should be always this number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZX2967_WDT_WRITEKEY (0x1234 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ZX2967_WDT_VAL_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ZX2967_WDT_DIV_DEFAULT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ZX2967_WDT_DEFAULT_TIMEOUT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ZX2967_WDT_MIN_TIMEOUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ZX2967_WDT_MAX_TIMEOUT 524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ZX2967_WDT_MAX_COUNT 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ZX2967_WDT_CLK_FREQ 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ZX2967_WDT_FLAG_REBOOT_MON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct zx2967_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct watchdog_device wdt_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return readl_relaxed(wdt->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void zx2967_wdt_refresh(struct zx2967_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Bit 4-5, 1 and 2: refresh config info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Bit 2-3, 1 and 2: refresh counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Bit 0-1, 1 and 2: refresh int-value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * we shift each group value between 1 and 2 to refresh all data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val ^= ZX2967_WDT_REFRESH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) zx2967_wdt_writel(wdt, ZX2967_WDT_REFRESH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val & ZX2967_WDT_VAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) zx2967_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int divisor = ZX2967_WDT_DIV_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) count = timeout * ZX2967_WDT_CLK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (count > divisor * ZX2967_WDT_MAX_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) count = DIV_ROUND_UP(count, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) zx2967_wdt_writel(wdt, ZX2967_WDT_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ZX2967_WDT_CFG_DIV(divisor) & ZX2967_WDT_VAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) zx2967_wdt_writel(wdt, ZX2967_WDT_LOAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) count & ZX2967_WDT_VAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) zx2967_wdt_refresh(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) wdd->timeout = (count * divisor) / ZX2967_WDT_CLK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void __zx2967_wdt_start(struct zx2967_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val |= ZX2967_WDT_START_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val & ZX2967_WDT_VAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void __zx2967_wdt_stop(struct zx2967_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~ZX2967_WDT_START_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val & ZX2967_WDT_VAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int zx2967_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) zx2967_wdt_set_timeout(wdd, wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __zx2967_wdt_start(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int zx2967_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __zx2967_wdt_stop(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int zx2967_wdt_keepalive(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) zx2967_wdt_refresh(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ZX2967_WDT_OPTIONS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct watchdog_info zx2967_wdt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .options = ZX2967_WDT_OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .identity = "zx2967 watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct watchdog_ops zx2967_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .start = zx2967_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .stop = zx2967_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .ping = zx2967_wdt_keepalive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .set_timeout = zx2967_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void zx2967_wdt_reset_sysctrl(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void __iomem *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int offset, mask, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct of_phandle_args out_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = of_parse_phandle_with_fixed_args(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "zte,wdt-reset-sysctrl", 3, 0, &out_args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) offset = out_args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) config = out_args.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mask = out_args.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) regmap = syscon_node_to_regmap(out_args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) of_node_put(out_args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) regmap_update_bits(regmap, offset, mask, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) of_node_put(out_args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void zx2967_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int zx2967_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct zx2967_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) wdt->wdt_device.info = &zx2967_wdt_ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wdt->wdt_device.ops = &zx2967_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) wdt->wdt_device.timeout = ZX2967_WDT_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) wdt->wdt_device.max_timeout = ZX2967_WDT_MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) wdt->wdt_device.min_timeout = ZX2967_WDT_MIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) wdt->wdt_device.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (IS_ERR(wdt->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return PTR_ERR(wdt->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) zx2967_wdt_reset_sysctrl(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) wdt->clock = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (IS_ERR(wdt->clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(dev, "failed to find watchdog clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return PTR_ERR(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = clk_prepare_enable(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = devm_add_action_or_reset(dev, zx2967_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_set_rate(wdt->clock, ZX2967_WDT_CLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rstc = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(dev, "failed to get rstc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) watchdog_set_drvdata(&wdt->wdt_device, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) watchdog_init_timeout(&wdt->wdt_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ZX2967_WDT_DEFAULT_TIMEOUT, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) watchdog_set_nowayout(&wdt->wdt_device, WATCHDOG_NOWAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = devm_watchdog_register_device(dev, &wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_info(dev, "watchdog enabled (timeout=%d sec, nowayout=%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) wdt->wdt_device.timeout, WATCHDOG_NOWAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct of_device_id zx2967_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { .compatible = "zte,zx296718-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_DEVICE_TABLE(of, zx2967_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct platform_driver zx2967_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .probe = zx2967_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "zx2967-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .of_match_table = of_match_ptr(zx2967_wdt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) module_platform_driver(zx2967_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_DESCRIPTION("ZTE zx2967 Watchdog Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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