Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-1.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	Industrial Computer Source WDT500/501 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	(c) Copyright 1995	CymruNET Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *				Innovation Centre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *				Singleton Park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *				Swansea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *				Wales
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *				UK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *				SA2 8PP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *	http://www.cymru.net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *	Release 0.04.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WDT_COUNT0		(io+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WDT_COUNT1		(io+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WDT_COUNT2		(io+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WDT_CR			(io+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WDT_SR			(io+4)	/* Start buzzer on PCI write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WDT_RT			(io+5)	/* Stop buzzer on PCI write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WDT_BUZZER		(io+6)	/* PCI only: rd=disable, wr=enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WDT_DC			(io+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* The following are only on the PCI card, they're outside of I/O space on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * the ISA card: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WDT_CLOCK		(io+12)	/* COUNT2: rd=16.67MHz, wr=2.0833MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* inverted opto isolated reset output: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WDT_OPTONOTRST		(io+13)	/* wr=enable, rd=disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* opto isolated reset output: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WDT_OPTORST		(io+14)	/* wr=enable, rd=disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* programmable outputs: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WDT_PROGOUT		(io+15)	/* wr=enable, rd=disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 							 /* FAN 501 500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WDC_SR_WCCR		1	/* Active low */ /*  X   X   X  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WDC_SR_TGOOD		2			 /*  X   X   -  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WDC_SR_ISOI0		4			 /*  X   X   X  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WDC_SR_ISII1		8			 /*  X   X   X  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WDC_SR_FANGOOD		16			 /*  X   -   -  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WDC_SR_PSUOVER		32	/* Active low */ /*  X   X   -  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WDC_SR_PSUUNDR		64	/* Active low */ /*  X   X   -  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WDC_SR_IRQ		128	/* Active low */ /*  X   X   X  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)