^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * w83627hf/thf WDT driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) Copyright 2013 Guenter Roeck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * converted to watchdog infrastructure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * added support for W83627THF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (c) Copyright 2003,2007 Pádraig Brady <P@draigBrady.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Based on advantechwdt.c which is based on wdt.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Original copyright messages:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * warranty for any of this software. This material is provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * "AS-IS" and at no charge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WATCHDOG_NAME "w83627hf/thf/hg/dhg WDT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int wdt_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int cr_wdt_timeout; /* WDT timeout register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int cr_wdt_control; /* WDT control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int cr_wdt_csr; /* WDT control & status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int wdt_cfg_enter = 0x87;/* key to unlock configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int wdt_cfg_leave = 0xAA;/* key to lock configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) nct6795, nct6796, nct6102, nct6116 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int timeout; /* in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) module_param(timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_PARM_DESC(timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "Watchdog timeout in seconds. 1 <= timeout <= 255, default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int early_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) module_param(early_disable, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Kernel methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WDT_EFIR (wdt_io+0) /* Extended Function Index Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (same as EFER) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define W83627HF_LD_WDT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define W83627HF_ID 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define W83627S_ID 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define W83697HF_ID 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define W83697UG_ID 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define W83637HF_ID 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define W83627THF_ID 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define W83687THF_ID 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define W83627EHF_ID 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define W83627DHG_ID 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define W83627UHG_ID 0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define W83667HG_ID 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define W83627DHG_P_ID 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define W83667HG_B_ID 0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NCT6775_ID 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NCT6776_ID 0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NCT6102_ID 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NCT6116_ID 0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NCT6779_ID 0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define NCT6791_ID 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NCT6792_ID 0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define NCT6793_ID 0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NCT6795_ID 0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NCT6796_ID 0xd4 /* also NCT9697D, NCT9698D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define W83627HF_WDT_TIMEOUT 0xf6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define W83697HF_WDT_TIMEOUT 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NCT6102D_WDT_TIMEOUT 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define W83627HF_WDT_CONTROL 0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define W83697HF_WDT_CONTROL 0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NCT6102D_WDT_CONTROL 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define W836X7HF_WDT_CSR 0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NCT6102D_WDT_CSR 0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void superio_outb(int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) outb(reg, WDT_EFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) outb(val, WDT_EFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline int superio_inb(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) outb(reg, WDT_EFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return inb(WDT_EFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int superio_enter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!request_muxed_region(wdt_io, 2, WATCHDOG_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) outb_p(wdt_cfg_enter, WDT_EFER); /* Enter extended function mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) outb_p(wdt_cfg_enter, WDT_EFER); /* Again according to manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void superio_select(int ld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) superio_outb(0x07, ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void superio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) outb_p(wdt_cfg_leave, WDT_EFER); /* Leave extended function mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) release_region(wdt_io, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned char t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) superio_select(W83627HF_LD_WDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* set CR30 bit 0 to activate GPIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) t = superio_inb(0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!(t & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) superio_outb(0x30, t | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case w83627hf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case w83627s:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) t = superio_inb(0x2B) & ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case w83697hf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Set pin 119 to WDTO# mode (= CR29, WDT0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) t = superio_inb(0x29) & ~0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) t |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) superio_outb(0x29, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case w83697ug:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Set pin 118 to WDTO# mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) t = superio_inb(0x2b) & ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) superio_outb(0x2b, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case w83627thf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) t = (superio_inb(0x2B) & ~0x08) | 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case w83627dhg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case w83627dhg_p:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) t = superio_inb(cr_wdt_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) t |= 0x02; /* enable the WDTO# output low pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * to the KBRST# pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) superio_outb(cr_wdt_control, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case w83637hf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case w83687thf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) superio_outb(0x2C, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case w83627ehf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case w83627uhg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case w83667hg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case w83667hg_b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case nct6775:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case nct6776:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case nct6779:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case nct6791:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case nct6792:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case nct6793:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case nct6795:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case nct6796:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case nct6102:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case nct6116:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * These chips have a fixed WDTO# output pin (W83627UHG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * or support more than one WDTO# output pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Don't touch its configuration, and hope the BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * does the right thing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) t = superio_inb(cr_wdt_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) t |= 0x02; /* enable the WDTO# output low pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * to the KBRST# pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) superio_outb(cr_wdt_control, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) t = superio_inb(cr_wdt_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (t != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (early_disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pr_warn("Stopping previously enabled watchdog until userland kicks in\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) superio_outb(cr_wdt_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pr_info("Watchdog already running. Resetting timeout to %d sec\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) wdog->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) superio_outb(cr_wdt_timeout, wdog->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* set second mode & disable keyboard turning off watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) t = superio_inb(cr_wdt_control) & ~0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) superio_outb(cr_wdt_control, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* reset trigger, disable keyboard & mouse turning off watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) t = superio_inb(cr_wdt_csr) & ~0xD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) superio_outb(cr_wdt_csr, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int wdt_set_time(unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) superio_select(W83627HF_LD_WDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) superio_outb(cr_wdt_timeout, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int wdt_start(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return wdt_set_time(wdog->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int wdt_stop(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return wdt_set_time(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int wdt_set_timeout(struct watchdog_device *wdog, unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wdog->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static unsigned int wdt_get_time(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) superio_select(W83627HF_LD_WDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) timeleft = superio_inb(cr_wdt_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Kernel Interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct watchdog_info wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .identity = "W83627HF Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct watchdog_ops wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .start = wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .stop = wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .set_timeout = wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .get_timeleft = wdt_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct watchdog_device wdt_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .info = &wdt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .ops = &wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .timeout = WATCHDOG_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .min_timeout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .max_timeout = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * The WDT needs to learn about soft shutdowns in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * turn the timebomb registers off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int wdt_find(int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cr_wdt_timeout = W83627HF_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cr_wdt_control = W83627HF_WDT_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cr_wdt_csr = W836X7HF_WDT_CSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) superio_select(W83627HF_LD_WDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) val = superio_inb(0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case W83627HF_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = w83627hf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case W83627S_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = w83627s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case W83697HF_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = w83697hf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cr_wdt_control = W83697HF_WDT_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case W83697UG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = w83697ug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cr_wdt_control = W83697HF_WDT_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case W83637HF_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = w83637hf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case W83627THF_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = w83627thf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case W83687THF_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = w83687thf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case W83627EHF_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = w83627ehf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case W83627DHG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = w83627dhg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case W83627DHG_P_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = w83627dhg_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case W83627UHG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = w83627uhg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case W83667HG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = w83667hg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case W83667HG_B_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = w83667hg_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case NCT6775_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = nct6775;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case NCT6776_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = nct6776;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case NCT6779_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = nct6779;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case NCT6791_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = nct6791;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case NCT6792_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = nct6792;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case NCT6793_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = nct6793;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case NCT6795_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = nct6795;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case NCT6796_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = nct6796;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case NCT6102_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = nct6102;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cr_wdt_timeout = NCT6102D_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cr_wdt_control = NCT6102D_WDT_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cr_wdt_csr = NCT6102D_WDT_CSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case NCT6116_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ret = nct6116;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) cr_wdt_timeout = NCT6102D_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cr_wdt_control = NCT6102D_WDT_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cr_wdt_csr = NCT6102D_WDT_CSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case 0xff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pr_err("Unsupported chip ID: 0x%02x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * On some systems, the NCT6791D comes with a companion chip and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * watchdog function is in this companion chip. We must use a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * unlocking sequence to access the companion chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int __init wdt_use_alt_key(const struct dmi_system_id *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) wdt_cfg_enter = 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) wdt_cfg_leave = 0xBB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct dmi_system_id wdt_dmi_table[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DMI_EXACT_MATCH(DMI_SYS_VENDOR, "INVES"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "INVES"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DMI_EXACT_MATCH(DMI_BOARD_NAME, "SHARKBAY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .callback = wdt_use_alt_key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int __init wdt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const char * const chip_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "W83627HF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "W83627S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "W83697HF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "W83697UG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "W83637HF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "W83627THF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "W83687THF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "W83627EHF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "W83627DHG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "W83627UHG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "W83667HG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "W83667DHG-P",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "W83667HG-B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "NCT6775",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "NCT6776",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "NCT6779",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "NCT6791",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "NCT6792",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "NCT6793",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "NCT6795",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "NCT6796",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "NCT6102",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "NCT6116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Apply system-specific quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dmi_check_system(wdt_dmi_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) wdt_io = 0x2e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) chip = wdt_find(0x2e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (chip < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) wdt_io = 0x4e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) chip = wdt_find(0x4e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (chip < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pr_info("WDT driver for %s Super I/O chip initialising\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) chip_name[chip]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) watchdog_init_timeout(&wdt_dev, timeout, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) watchdog_set_nowayout(&wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) watchdog_stop_on_reboot(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = w83627hf_init(&wdt_dev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pr_err("failed to initialize watchdog (err=%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = watchdog_register_device(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pr_info("initialized. timeout=%d sec (nowayout=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) wdt_dev.timeout, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void __exit wdt_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) watchdog_unregister_device(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) module_init(wdt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) module_exit(wdt_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_AUTHOR("Pádraig Brady <P@draigBrady.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_DESCRIPTION("w83627hf/thf WDT driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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