^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * VIA Chipset Watchdog Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Sigfox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Marc Vertes <marc.vertes@sigfox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on a preliminary version from Harald Welte <HaraldWelte@viatech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Timer code by Wim Van Sebroeck <wim@iguana.be>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Caveat: PnP must be enabled in BIOS to allow full access to watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * control registers. If not, the watchdog must be configured in BIOS manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Configuration registers relative to the pci device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIA_WDT_MMIO_BASE 0xe8 /* MMIO region base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VIA_WDT_CONF 0xec /* watchdog enable state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Relevant bits for the VIA_WDT_CONF register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VIA_WDT_CONF_ENABLE 0x01 /* 1: enable watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The MMIO region contains the watchdog control register and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * hardware timer counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VIA_WDT_MMIO_LEN 8 /* MMIO region length in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIA_WDT_CTL 0 /* MMIO addr+0: state/control reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIA_WDT_COUNT 4 /* MMIO addr+4: timer counter reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Bits for the VIA_WDT_CTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VIA_WDT_RUNNING 0x01 /* 0: stop, 1: running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VIA_WDT_FIRED 0x02 /* 1: restarted by expired watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VIA_WDT_PWROFF 0x04 /* 0: reset, 1: poweroff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VIA_WDT_DISABLED 0x08 /* 1: timer is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VIA_WDT_TRIGGER 0x80 /* 1: start a new countdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Hardware heartbeat in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WDT_HW_HEARTBEAT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Timer heartbeat (500ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WDT_HEARTBEAT (HZ/2) /* should be <= ((WDT_HW_HEARTBEAT*HZ)/2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* User space timeout in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WDT_TIMEOUT_MAX 1023 /* approx. 17 min. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WDT_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int timeout = WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) module_param(timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, between 1 and 1023 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "(default = " __MODULE_STRING(WDT_TIMEOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "(default = " __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct watchdog_device wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct resource wdt_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void __iomem *wdt_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static unsigned int mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void wdt_timer_tick(struct timer_list *unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static DEFINE_TIMER(timer, wdt_timer_tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* The timer that pings the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static unsigned long next_heartbeat; /* the next_heartbeat for the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void wdt_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int ctl = readl(wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel(ctl | VIA_WDT_TRIGGER, wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Timer tick: the timer will make sure that the watchdog timer hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * is being reset in time. The conditions to do this are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 1) the watchdog timer has been started and /dev/watchdog is open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * and there is still time left before userspace should send the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * next heartbeat/ping. (note: the internal heartbeat is much smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * then the external/userspace heartbeat).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 2) the watchdog timer has been stopped by userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void wdt_timer_tick(struct timer_list *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (time_before(jiffies, next_heartbeat) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (!watchdog_active(&wdt_dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) wdt_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mod_timer(&timer, jiffies + WDT_HEARTBEAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pr_crit("I will reboot your machine !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* calculate when the next userspace timeout will be */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) next_heartbeat = jiffies + wdd->timeout * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int ctl = readl(wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(wdd->timeout, wdt_mem + VIA_WDT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(ctl | VIA_WDT_RUNNING | VIA_WDT_TRIGGER, wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) wdt_ping(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mod_timer(&timer, jiffies + WDT_HEARTBEAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int ctl = readl(wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(ctl & ~VIA_WDT_RUNNING, wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int new_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(new_timeout, wdt_mem + VIA_WDT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wdd->timeout = new_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct watchdog_info wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .identity = "VIA watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .options = WDIOF_CARDRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct watchdog_ops wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .start = wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .stop = wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .ping = wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .set_timeout = wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct watchdog_device wdt_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .info = &wdt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ops = &wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .min_timeout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .max_timeout = WDT_TIMEOUT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int wdt_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned char conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (pci_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(&pdev->dev, "cannot enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Allocate a MMIO region which contains watchdog control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * and counter, then configure the watchdog to use this region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * This is possible only if PnP is properly enabled in BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * If not, the watchdog must be configured in BIOS manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (allocate_resource(&iomem_resource, &wdt_res, VIA_WDT_MMIO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0xf0000000, 0xffffff00, 0xff, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(&pdev->dev, "MMIO allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto err_out_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pci_write_config_dword(pdev, VIA_WDT_MMIO_BASE, wdt_res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pci_read_config_byte(pdev, VIA_WDT_CONF, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) conf |= VIA_WDT_CONF_ENABLE | VIA_WDT_CONF_MMIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pci_write_config_byte(pdev, VIA_WDT_CONF, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_info(&pdev->dev, "VIA Chipset watchdog MMIO: %x\n", mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(&pdev->dev, "MMIO setting failed. Check BIOS.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto err_out_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!request_mem_region(mmio, VIA_WDT_MMIO_LEN, "via_wdt")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(&pdev->dev, "MMIO region busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto err_out_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) wdt_mem = ioremap(mmio, VIA_WDT_MMIO_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (wdt_mem == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&pdev->dev, "cannot remap VIA wdt MMIO registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto err_out_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (timeout < 1 || timeout > WDT_TIMEOUT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) timeout = WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) wdt_dev.timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wdt_dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) watchdog_set_nowayout(&wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (readl(wdt_mem) & VIA_WDT_FIRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) wdt_dev.bootstatus |= WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = watchdog_register_device(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* start triggering, in case of watchdog already enabled by BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mod_timer(&timer, jiffies + WDT_HEARTBEAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) err_out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) iounmap(wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err_out_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) release_mem_region(mmio, VIA_WDT_MMIO_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) err_out_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) release_resource(&wdt_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err_out_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void wdt_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) watchdog_unregister_device(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) del_timer_sync(&timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) iounmap(wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) release_mem_region(mmio, VIA_WDT_MMIO_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) release_resource(&wdt_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct pci_device_id wdt_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct pci_driver wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "via_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .id_table = wdt_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .probe = wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .remove = wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) module_pci_driver(wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_AUTHOR("Marc Vertes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DESCRIPTION("Driver for watchdog timer on VIA chipset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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