^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Watchdog driver for the UniPhier watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) Copyright 2014 Panasonic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (c) Copyright 2016 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* WDT timer setting register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WDTTIMSET 0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WDTTIMSET_PERIOD_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WDTTIMSET_PERIOD_1_SEC (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* WDT reset selection register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WDTRSTSEL 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WDTRSTSEL_RSTSEL_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WDTRSTSEL_RSTSEL_BOTH (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WDTRSTSEL_RSTSEL_IRQ_ONLY (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* WDT control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WDTCTRL 0x300c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WDTCTRL_STATUS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WDTCTRL_CLEAR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WDTCTRL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SEC_TO_WDTTIMSET_PRD(sec) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (ilog2(sec) + WDTTIMSET_PERIOD_1_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WDTST_TIMEOUT 1000 /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WDT_DEFAULT_TIMEOUT 64 /* Default is 64 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WDT_PERIOD_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WDT_PERIOD_MAX 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static unsigned int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct uniphier_wdt_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct watchdog_device wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * UniPhier Watchdog operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int uniphier_watchdog_ping(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Clear counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = regmap_write_bits(wdev->regmap, WDTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) WDTCTRL_CLEAR, WDTCTRL_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * As SoC specification, after clear counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * it needs to wait until counter status is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = regmap_read_poll_timeout(wdev->regmap, WDTCTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) (val & WDTCTRL_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0, WDTST_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int __uniphier_watchdog_start(struct regmap *regmap, unsigned int sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = regmap_read_poll_timeout(regmap, WDTCTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) !(val & WDTCTRL_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0, WDTST_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Setup period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = regmap_write(regmap, WDTTIMSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SEC_TO_WDTTIMSET_PRD(sec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Enable and clear watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = regmap_write(regmap, WDTCTRL, WDTCTRL_ENABLE | WDTCTRL_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * As SoC specification, after clear counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * it needs to wait until counter status is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = regmap_read_poll_timeout(regmap, WDTCTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (val & WDTCTRL_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0, WDTST_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int __uniphier_watchdog_stop(struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Disable and stop watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return regmap_write_bits(regmap, WDTCTRL, WDTCTRL_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int __uniphier_watchdog_restart(struct regmap *regmap, unsigned int sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = __uniphier_watchdog_stop(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return __uniphier_watchdog_start(regmap, sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int uniphier_watchdog_start(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int tmp_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tmp_timeout = roundup_pow_of_two(w->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return __uniphier_watchdog_start(wdev->regmap, tmp_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int uniphier_watchdog_stop(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return __uniphier_watchdog_stop(wdev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int uniphier_watchdog_set_timeout(struct watchdog_device *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int tmp_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tmp_timeout = roundup_pow_of_two(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (tmp_timeout == w->timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (watchdog_active(w)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = __uniphier_watchdog_restart(wdev->regmap, tmp_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) w->timeout = tmp_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Kernel Interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct watchdog_info uniphier_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .identity = "uniphier-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .options = WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) WDIOF_OVERHEAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct watchdog_ops uniphier_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .start = uniphier_watchdog_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .stop = uniphier_watchdog_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .ping = uniphier_watchdog_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .set_timeout = uniphier_watchdog_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int uniphier_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct uniphier_wdt_dev *wdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) parent = of_get_parent(dev->of_node); /* parent should be syscon node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) regmap = syscon_node_to_regmap(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) wdev->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) wdev->wdt_dev.info = &uniphier_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) wdev->wdt_dev.ops = &uniphier_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) wdev->wdt_dev.max_timeout = WDT_PERIOD_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) wdev->wdt_dev.min_timeout = WDT_PERIOD_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) wdev->wdt_dev.timeout = WDT_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) wdev->wdt_dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) watchdog_init_timeout(&wdev->wdt_dev, timeout, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) watchdog_set_nowayout(&wdev->wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) watchdog_stop_on_reboot(&wdev->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) watchdog_set_drvdata(&wdev->wdt_dev, wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) uniphier_watchdog_stop(&wdev->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = regmap_write(wdev->regmap, WDTRSTSEL, WDTRSTSEL_RSTSEL_BOTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = devm_watchdog_register_device(dev, &wdev->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_info(dev, "watchdog driver (timeout=%d sec, nowayout=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) wdev->wdt_dev.timeout, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct of_device_id uniphier_wdt_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .compatible = "socionext,uniphier-wdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DEVICE_TABLE(of, uniphier_wdt_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct platform_driver uniphier_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .probe = uniphier_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "uniphier-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .of_match_table = uniphier_wdt_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) module_platform_driver(uniphier_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) module_param(timeout, uint, 0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_PARM_DESC(timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "Watchdog timeout seconds in power of 2. (0 < timeout < 128, default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) module_param(nowayout, bool, 0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_DESCRIPTION("UniPhier Watchdog Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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