Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* minimum and maximum watchdog trigger timeout, in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MIN_WDT_TIMEOUT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MAX_WDT_TIMEOUT			255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Base of the WDT registers, from the timer base address.  There are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * actually 5 watchdogs that can be configured (by pairing with an available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * This driver only configures the first watchdog (WDT ID 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define WDT_BASE			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define WDT_ID				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * Register base of the timer that's selected for pairing with the watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * This driver arbitrarily uses timer 5, which is currently unused by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * other drivers (in particular, the Tegra clocksource driver).  If this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * needs to change, take care that the new timer is not used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * clocksource driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define WDT_TIMER_BASE			0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WDT_TIMER_ID			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* WDT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WDT_CFG				0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WDT_CFG_PERIOD_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WDT_CFG_PERIOD_MASK		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WDT_CFG_INT_EN			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WDT_CFG_PMC2CAR_RST_EN		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WDT_STS				0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WDT_STS_COUNT_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WDT_STS_COUNT_MASK		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WDT_STS_EXP_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WDT_STS_EXP_MASK		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WDT_CMD				0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WDT_CMD_START_COUNTER		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WDT_CMD_DISABLE_COUNTER		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WDT_UNLOCK			(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WDT_UNLOCK_PATTERN		(0xc45a << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Timer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TIMER_PTV			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TIMER_EN			(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TIMER_PERIODIC			(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct tegra_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct watchdog_device	wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	void __iomem		*wdt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void __iomem		*tmr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define WDT_HEARTBEAT 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int heartbeat = WDT_HEARTBEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) MODULE_PARM_DESC(heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	"Watchdog heartbeats in seconds. (default = "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__MODULE_STRING(WDT_HEARTBEAT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	"Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int tegra_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * This thing has a fixed 1MHz clock.  Normally, we would set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * period to 1 second by writing 1000000ul, but the watchdog system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * reset actually occurs on the 4th expiration of this counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * so we set the period to 1/4 of this amount.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	val = 1000000ul / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	val |= (TIMER_EN | TIMER_PERIODIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	writel(val, wdt->tmr_regs + TIMER_PTV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * Set number of periods and start counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * Interrupt handler is not required for user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * WDT accesses, since the caller is responsible to ping the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * WDT to reset the counter before expiration, through ioctls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	val = WDT_TIMER_ID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	      (wdd->timeout << WDT_CFG_PERIOD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	      WDT_CFG_PMC2CAR_RST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	writel(val, wdt->wdt_regs + WDT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int tegra_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	writel(0, wdt->tmr_regs + TIMER_PTV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int tegra_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int tegra_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				 unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (watchdog_active(wdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		tegra_wdt_stop(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return tegra_wdt_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static unsigned int tegra_wdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	val = readl(wdt->wdt_regs + WDT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* Current countdown (from timeout) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* Number of expirations (we are waiting for the 4th expiration) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * The entire thing is divided by 4 because we are ticking down 4 times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * faster due to needing to wait for the 4th expiration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return (((3 - exp) * wdd->timeout) + count) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct watchdog_info tegra_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.options	= WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			  WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			  WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.firmware_version = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.identity	= "Tegra Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct watchdog_ops tegra_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.start = tegra_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.stop = tegra_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.ping = tegra_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.set_timeout = tegra_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.get_timeleft = tegra_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int tegra_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct tegra_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* This is the timer base. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * Allocate our watchdog driver data, which has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 * struct watchdog_device nested within it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Initialize struct tegra_wdt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	wdt->wdt_regs = regs + WDT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	wdt->tmr_regs = regs + WDT_TIMER_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* Initialize struct watchdog_device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	wdd = &wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	wdd->timeout = heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	wdd->info = &tegra_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	wdd->ops = &tegra_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	wdd->min_timeout = MIN_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	wdd->max_timeout = MAX_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	watchdog_set_drvdata(wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	watchdog_set_nowayout(wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	watchdog_stop_on_unregister(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = devm_watchdog_register_device(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	dev_info(dev, "initialized (heartbeat = %d sec, nowayout = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		 heartbeat, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int tegra_wdt_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct tegra_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		tegra_wdt_stop(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int tegra_wdt_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct tegra_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		tegra_wdt_start(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct of_device_id tegra_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	{ .compatible = "nvidia,tegra30-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_DEVICE_TABLE(of, tegra_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct dev_pm_ops tegra_wdt_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	SET_SYSTEM_SLEEP_PM_OPS(tegra_wdt_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				tegra_wdt_runtime_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct platform_driver tegra_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.probe		= tegra_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.name	= "tegra-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.pm	= &tegra_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.of_match_table = tegra_wdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) module_platform_driver(tegra_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_AUTHOR("NVIDIA Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_DESCRIPTION("Tegra Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_LICENSE("GPL v2");