^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for STM32 Independent Watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver is based on tegra_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* IWDG registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IWDG_KR 0x00 /* Key register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IWDG_PR 0x04 /* Prescaler Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IWDG_RLR 0x08 /* ReLoad Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IWDG_SR 0x0C /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IWDG_WINR 0x10 /* Windows Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* IWDG_KR register bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define KR_KEY_EWA 0x5555 /* write access enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define KR_KEY_DWA 0x0000 /* write access disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* IWDG_PR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PR_MIN BIT(PR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* IWDG_RLR register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RLR_MIN 0x2 /* min value recommended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RLR_MAX GENMASK(11, 0) /* max value of reload register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* IWDG_SR register bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SR_PVU BIT(0) /* Watchdog prescaler value update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SR_RVU BIT(1) /* Watchdog counter reload value update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* set timeout to 100000 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLEEP_US 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct stm32_iwdg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool has_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 max_prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct stm32_iwdg_data stm32_iwdg_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .has_pclk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .max_prescaler = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .has_pclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .max_prescaler = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct stm32_iwdg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const struct stm32_iwdg_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk *clk_lsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *clk_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline u32 reg_read(void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static inline void reg_write(void __iomem *base, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel_relaxed(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int stm32_iwdg_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_dbg(wdd->parent, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tout = clamp_t(unsigned int, wdd->timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) presc = roundup_pow_of_two(presc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* enable write access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* set prescaler & reload registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg_write(wdt->regs, IWDG_PR, iwdg_pr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* wait for the registers to be updated (max 100ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) !(iwdg_sr & (SR_PVU | SR_RVU)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SLEEP_US, TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* reload watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int stm32_iwdg_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_dbg(wdd->parent, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* reload watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (watchdog_active(wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return stm32_iwdg_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void stm32_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int stm32_iwdg_clk_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct stm32_iwdg *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) wdt->clk_lsi = devm_clk_get(dev, "lsi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (IS_ERR(wdt->clk_lsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(dev, "Unable to get lsi clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return PTR_ERR(wdt->clk_lsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* optional peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (wdt->data->has_pclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) wdt->clk_pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (IS_ERR(wdt->clk_pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_err(dev, "Unable to get pclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return PTR_ERR(wdt->clk_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = clk_prepare_enable(wdt->clk_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(dev, "Unable to prepare pclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = devm_add_action_or_reset(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) stm32_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) wdt->clk_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = clk_prepare_enable(wdt->clk_lsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(dev, "Unable to prepare lsi clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) wdt->clk_lsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) wdt->rate = clk_get_rate(wdt->clk_lsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct watchdog_info stm32_iwdg_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .options = WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .identity = "STM32 Independent Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct watchdog_ops stm32_iwdg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .start = stm32_iwdg_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .ping = stm32_iwdg_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .set_timeout = stm32_iwdg_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct of_device_id stm32_iwdg_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { /* end node */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int stm32_iwdg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct stm32_iwdg *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) wdt->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!wdt->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* This is the timer base. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) wdt->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (IS_ERR(wdt->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(dev, "Could not get resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return PTR_ERR(wdt->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = stm32_iwdg_clk_init(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Initialize struct watchdog_device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) wdd = &wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) wdd->info = &stm32_iwdg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) wdd->ops = &stm32_iwdg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 1000) / wdt->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) watchdog_set_drvdata(wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) watchdog_init_timeout(wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * (Means U-Boot/bootloaders leaves the watchdog running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * When we get here we should make a decision to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * any side effects before user space daemon will take care of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * The best option, taking into consideration that there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * way to read values back from hardware, is to enforce watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * being run with deterministic values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = stm32_iwdg_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Make sure the watchdog is serviced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) set_bit(WDOG_HW_RUNNING, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = devm_watchdog_register_device(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct platform_driver stm32_iwdg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .probe = stm32_iwdg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .name = "iwdg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .of_match_table = of_match_ptr(stm32_iwdg_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) module_platform_driver(stm32_iwdg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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