^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Spreadtrum watchdog driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPRD_WDT_LOAD_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_WDT_LOAD_HIGH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_WDT_CTRL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPRD_WDT_INT_CLR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_WDT_INT_RAW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPRD_WDT_INT_MSK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_WDT_CNT_LOW 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_WDT_CNT_HIGH 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPRD_WDT_LOCK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_WDT_IRQ_LOAD_LOW 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_WDT_IRQ_LOAD_HIGH 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* WDT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPRD_WDT_INT_EN_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPRD_WDT_CNT_EN_BIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_WDT_NEW_VER_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPRD_WDT_RST_EN_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* WDT_INT_CLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPRD_WDT_INT_CLEAR_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPRD_WDT_RST_CLEAR_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* WDT_INT_RAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPRD_WDT_INT_RAW_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPRD_WDT_RST_RAW_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPRD_WDT_LD_BUSY_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* 1s equal to 32768 counter steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPRD_WDT_CNT_STEP 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPRD_WDT_UNLOCK_KEY 0xe551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPRD_WDT_MIN_TIMEOUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPRD_WDT_MAX_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPRD_WDT_CNT_HIGH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPRD_WDT_LOW_VALUE_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPRD_WDT_LOAD_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct sprd_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk *enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk *rtc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline struct sprd_wdt *to_sprd_wdt(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return container_of(wdd, struct sprd_wdt, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline void sprd_wdt_lock(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel_relaxed(0x0, addr + SPRD_WDT_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline void sprd_wdt_unlock(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel_relaxed(SPRD_WDT_UNLOCK_KEY, addr + SPRD_WDT_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static irqreturn_t sprd_wdt_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct sprd_wdt *wdt = (struct sprd_wdt *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) sprd_wdt_unlock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sprd_wdt_lock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) watchdog_notify_pretimeout(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static u32 sprd_wdt_get_cnt_value(struct sprd_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SPRD_WDT_CNT_HIGH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SPRD_WDT_LOW_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int sprd_wdt_load_value(struct sprd_wdt *wdt, u32 timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 pretimeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 val, delay_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 tmr_step = timeout * SPRD_WDT_CNT_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 prtmr_step = pretimeout * SPRD_WDT_CNT_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Waiting the load value operation done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * it needs two or three RTC clock cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!(val & SPRD_WDT_LD_BUSY_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } while (delay_cnt++ < SPRD_WDT_LOAD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (delay_cnt >= SPRD_WDT_LOAD_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sprd_wdt_unlock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel_relaxed((tmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SPRD_WDT_LOW_VALUE_MASK, wdt->base + SPRD_WDT_LOAD_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel_relaxed((tmr_step & SPRD_WDT_LOW_VALUE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) wdt->base + SPRD_WDT_LOAD_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed((prtmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SPRD_WDT_LOW_VALUE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) wdt->base + SPRD_WDT_IRQ_LOAD_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel_relaxed(prtmr_step & SPRD_WDT_LOW_VALUE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) wdt->base + SPRD_WDT_IRQ_LOAD_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) sprd_wdt_lock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int sprd_wdt_enable(struct sprd_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = clk_prepare_enable(wdt->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = clk_prepare_enable(wdt->rtc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_disable_unprepare(wdt->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) sprd_wdt_unlock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val |= SPRD_WDT_NEW_VER_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) sprd_wdt_lock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void sprd_wdt_disable(void *_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct sprd_wdt *wdt = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sprd_wdt_unlock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sprd_wdt_lock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clk_disable_unprepare(wdt->rtc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clk_disable_unprepare(wdt->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int sprd_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct sprd_wdt *wdt = to_sprd_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = sprd_wdt_load_value(wdt, wdd->timeout, wdd->pretimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sprd_wdt_unlock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= SPRD_WDT_CNT_EN_BIT | SPRD_WDT_INT_EN_BIT | SPRD_WDT_RST_EN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sprd_wdt_lock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) set_bit(WDOG_HW_RUNNING, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int sprd_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct sprd_wdt *wdt = to_sprd_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sprd_wdt_unlock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) val &= ~(SPRD_WDT_CNT_EN_BIT | SPRD_WDT_RST_EN_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SPRD_WDT_INT_EN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) sprd_wdt_lock(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int sprd_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct sprd_wdt *wdt = to_sprd_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (timeout == wdd->timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return sprd_wdt_load_value(wdt, timeout, wdd->pretimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int sprd_wdt_set_pretimeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 new_pretimeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct sprd_wdt *wdt = to_sprd_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (new_pretimeout < wdd->min_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) wdd->pretimeout = new_pretimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return sprd_wdt_load_value(wdt, wdd->timeout, new_pretimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static u32 sprd_wdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct sprd_wdt *wdt = to_sprd_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) val = sprd_wdt_get_cnt_value(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return val / SPRD_WDT_CNT_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct watchdog_ops sprd_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .start = sprd_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .stop = sprd_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .set_timeout = sprd_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .set_pretimeout = sprd_wdt_set_pretimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .get_timeleft = sprd_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct watchdog_info sprd_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .options = WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) WDIOF_PRETIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .identity = "Spreadtrum Watchdog Timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int sprd_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct sprd_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) wdt->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (IS_ERR(wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return PTR_ERR(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) wdt->enable = devm_clk_get(dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (IS_ERR(wdt->enable)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(dev, "can't get the enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return PTR_ERR(wdt->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) wdt->rtc_enable = devm_clk_get(dev, "rtc_enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (IS_ERR(wdt->rtc_enable)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(dev, "can't get the rtc enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return PTR_ERR(wdt->rtc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) wdt->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (wdt->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return wdt->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = devm_request_irq(dev, wdt->irq, sprd_wdt_isr, IRQF_NO_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "sprd-wdt", (void *)wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "failed to register irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) wdt->wdd.info = &sprd_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) wdt->wdd.ops = &sprd_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) wdt->wdd.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) wdt->wdd.min_timeout = SPRD_WDT_MIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) wdt->wdd.max_timeout = SPRD_WDT_MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) wdt->wdd.timeout = SPRD_WDT_MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = sprd_wdt_enable(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(dev, "failed to enable wdt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = devm_add_action_or_reset(dev, sprd_wdt_disable, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(dev, "Failed to add wdt disable action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) watchdog_init_timeout(&wdt->wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = devm_watchdog_register_device(dev, &wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) sprd_wdt_disable(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int __maybe_unused sprd_wdt_pm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct sprd_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sprd_wdt_stop(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) sprd_wdt_disable(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int __maybe_unused sprd_wdt_pm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct sprd_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = sprd_wdt_enable(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = sprd_wdt_start(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct dev_pm_ops sprd_wdt_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SET_SYSTEM_SLEEP_PM_OPS(sprd_wdt_pm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sprd_wdt_pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct of_device_id sprd_wdt_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .compatible = "sprd,sp9860-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_DEVICE_TABLE(of, sprd_wdt_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct platform_driver sprd_watchdog_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .probe = sprd_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = "sprd-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .of_match_table = sprd_wdt_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .pm = &sprd_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) module_platform_driver(sprd_watchdog_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_DESCRIPTION("Spreadtrum Watchdog Timer Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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