^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/char/watchdog/sp805-wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Watchdog driver for ARM SP805 watchdog module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License version 2 or later. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* default timeout in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DEFAULT_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MODULE_NAME "sp805-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* watchdog register offsets and masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WDTLOAD 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LOAD_MIN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LOAD_MAX 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WDTVALUE 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WDTCONTROL 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* control register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define INT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RESET_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WDTINTCLR 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WDTRIS 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WDTMIS 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INT_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WDTLOCK 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UNLOCK 0x1ACCE551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LOCK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct sp805_wdt: sp805 wdt device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @wdd: instance of struct watchdog_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @lock: spin lock protecting dev structure and io access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @base: base address of wdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @clk: clock structure of wdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @adev: amba device structure of wdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @status: current status of wdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @load_val: load value to be set for current timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct sp805_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct amba_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int load_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "Set to 1 to keep watchdog running after device release");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* returns true if wdt is running; otherwise returns false */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static bool wdt_is_running(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* This routine finds load value that will reset system in required timout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u64 load, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rate = wdt->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * sp805 runs counter with given value twice, after the end of first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * counter it gives an interrupt and then starts counter again. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * interrupt already occurred then it resets the system. This is why
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * load is half of what should be required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) load = div_u64(rate, 2) * timeout - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) load = (load > LOAD_MAX) ? LOAD_MAX : load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) load = (load < LOAD_MIN) ? LOAD_MIN : load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) spin_lock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) wdt->load_val = load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* roundup timeout to closest positive integer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) spin_unlock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* returns number of seconds left for reset to occur */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned int wdt_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u64 load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spin_lock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) load = readl_relaxed(wdt->base + WDTVALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) load += wdt->load_val + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_unlock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return div_u64(load, wdt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel_relaxed(0, wdt->base + WDTCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel_relaxed(0, wdt->base + WDTLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Flush posted writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) readl_relaxed(wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int wdt_config(struct watchdog_device *wdd, bool ping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!ping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = clk_prepare_enable(wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(&wdt->adev->dev, "clock enable fail");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_lock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!ping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) WDTCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel_relaxed(LOCK, wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Flush posted writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) readl_relaxed(wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_unlock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return wdt_config(wdd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* enables watchdog timers reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int wdt_enable(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return wdt_config(wdd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* disables watchdog timers reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int wdt_disable(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_lock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) writel_relaxed(0, wdt->base + WDTCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel_relaxed(LOCK, wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Flush posted writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) readl_relaxed(wdt->base + WDTLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_unlock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_disable_unprepare(wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct watchdog_info wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .identity = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct watchdog_ops wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .start = wdt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .stop = wdt_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .ping = wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .set_timeout = wdt_setload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .get_timeleft = wdt_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .restart = wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct sp805_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!wdt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (IS_ERR(wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return PTR_ERR(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (adev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) wdt->clk = devm_clk_get(&adev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (IS_ERR(wdt->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(&adev->dev, "Clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return PTR_ERR(wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) wdt->rate = clk_get_rate(wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } else if (has_acpi_companion(&adev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * When Driver probe with ACPI device, clock devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * are not available, so watchdog rate get from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * clock-frequency property given in _DSD object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) device_property_read_u64(&adev->dev, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &wdt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!wdt->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(&adev->dev, "no clock-frequency property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) wdt->adev = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) wdt->wdd.info = &wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) wdt->wdd.ops = &wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wdt->wdd.parent = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_lock_init(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) watchdog_set_nowayout(&wdt->wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) watchdog_set_drvdata(&wdt->wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) watchdog_set_restart_priority(&wdt->wdd, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * If 'timeout-sec' devicetree property is specified, use that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Otherwise, use DEFAULT_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) wdt->wdd.timeout = DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wdt_setload(&wdt->wdd, wdt->wdd.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * If HW is already running, enable/reset the wdt and set the running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * bit to tell the wdt subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (wdt_is_running(&wdt->wdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) wdt_enable(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = watchdog_register_device(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) amba_set_drvdata(adev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_info(&adev->dev, "registration successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(&adev->dev, "Probe Failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void sp805_wdt_remove(struct amba_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct sp805_wdt *wdt = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) watchdog_unregister_device(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) watchdog_set_drvdata(&wdt->wdd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int __maybe_unused sp805_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct sp805_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return wdt_disable(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int __maybe_unused sp805_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct sp805_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return wdt_enable(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sp805_wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct amba_id sp805_wdt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .id = 0x00141805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .mask = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct amba_driver sp805_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .pm = &sp805_wdt_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .id_table = sp805_wdt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .probe = sp805_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .remove = sp805_wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) module_amba_driver(sp805_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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