Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	sp5100_tco:	TCO timer driver for sp5100 chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	(c) Copyright 2009 Google Inc., All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	TCO timer driver for sp5100 chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * Some address definitions for the Watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SP5100_WDT_MEM_MAP_SIZE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SP5100_WDT_CONTROL(base)	((base) + 0x00) /* Watchdog Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SP5100_WDT_COUNT(base)		((base) + 0x04) /* Watchdog Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SP5100_WDT_START_STOP_BIT	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SP5100_WDT_FIRED		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SP5100_WDT_ACTION_RESET		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SP5100_WDT_DISABLED		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SP5100_WDT_TRIGGER_BIT		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SP5100_PM_IOPORTS_SIZE		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * These two IO registers are hardcoded and there doesn't seem to be a way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * read them from a register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*  For SP5100/SB7x0/SB8x0 chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SP5100_IO_PM_INDEX_REG		0xCD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SP5100_IO_PM_DATA_REG		0xCD7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* For SP5100/SB7x0 chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SP5100_SB_RESOURCE_MMIO_BASE	0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SP5100_PM_WATCHDOG_CONTROL	0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SP5100_PM_WATCHDOG_BASE		0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SP5100_PCI_WATCHDOG_MISC_REG	0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SP5100_PCI_WATCHDOG_DECODE_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SP5100_PM_WATCHDOG_DISABLE	((u8)BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SP5100_PM_WATCHDOG_SECOND_RES	GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SP5100_DEVNAME			"SP5100 TCO"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*  For SB8x0(or later) chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SB800_PM_ACPI_MMIO_EN		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SB800_PM_WATCHDOG_CONTROL	0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SB800_PM_WATCHDOG_BASE		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SB800_PM_WATCHDOG_CONFIG	0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SB800_PCI_WATCHDOG_DECODE_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SB800_PM_WATCHDOG_DISABLE	((u8)BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SB800_PM_WATCHDOG_SECOND_RES	GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SB800_ACPI_MMIO_DECODE_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SB800_ACPI_MMIO_SEL		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SB800_PM_WDT_MMIO_OFFSET	0xB00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SB800_DEVNAME			"SB800 TCO"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* For recent chips with embedded FCH (rev 40+) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EFCH_PM_DECODEEN		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EFCH_PM_DECODEEN_WDT_TMREN	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EFCH_PM_DECODEEN3		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EFCH_PM_DECODEEN_SECOND_RES	GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EFCH_PM_WATCHDOG_DISABLE	((u8)GENMASK(3, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EFCH_PM_WDT_ADDR		0xfeb00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EFCH_PM_ISACONTROL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EFCH_PM_ISACONTROL_MMIOEN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EFCH_PM_ACPI_MMIO_ADDR		0xfed80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EFCH_PM_ACPI_MMIO_WDT_OFFSET	0x00000b00