^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sp5100_tco : TCO timer driver for sp5100 chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) Copyright 2009 Google Inc., All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on i8xx_tco.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * https://www.kernelconcepts.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * AMD Publication 45482 "AMD SB800-Series Southbridges Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Reference Guide"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * for AMD Family 16h Models 00h-0Fh Processors"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * for AMD Family 16h Models 30h-3Fh Processors"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * for AMD Family 17h Model 18h, Revision B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Processors (PUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * for AMD Family 17h Model 20h, Revision A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Processors (PUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Includes, defines, variables, module parameters, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "sp5100_tco.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TCO_DRIVER_NAME "sp5100-tco"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* internal variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum tco_reg_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) sp5100, sb800, efch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct sp5100_tco {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *tcobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum tco_reg_layout tco_reg_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* the watchdog platform device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct platform_device *sp5100_tco_platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* the associated PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct pci_dev *sp5100_tco_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Some TCO specific functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (dev->vendor == PCI_VENDOR_ID_ATI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev->revision < 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return sp5100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev->revision >= 0x41) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev->revision >= 0x49))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return efch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return sb800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int tco_timer_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val = readl(SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val |= SP5100_WDT_START_STOP_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(val, SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int tco_timer_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = readl(SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~SP5100_WDT_START_STOP_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(val, SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int tco_timer_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val = readl(SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val |= SP5100_WDT_TRIGGER_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(val, SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int tco_timer_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Write new heartbeat to watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(t, SP5100_WDT_COUNT(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) wdd->timeout = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static u8 sp5100_tco_read_pm_reg8(u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) outb(index, SP5100_IO_PM_INDEX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return inb(SP5100_IO_PM_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) outb(index, SP5100_IO_PM_INDEX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = inb(SP5100_IO_PM_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val &= reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) outb(val, SP5100_IO_PM_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void tco_timer_enable(struct sp5100_tco *tco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (tco->tco_reg_layout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case sb800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* For SB800 or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Set the Watchdog timer resolution to 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0xff, SB800_PM_WATCHDOG_SECOND_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Enable watchdog decode bit and watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ~SB800_PM_WATCHDOG_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SB800_PCI_WATCHDOG_DECODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case sp5100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* For SP5100 or SB7x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Enable watchdog decode bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pci_read_config_dword(sp5100_tco_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SP5100_PCI_WATCHDOG_MISC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= SP5100_PCI_WATCHDOG_DECODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pci_write_config_dword(sp5100_tco_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SP5100_PCI_WATCHDOG_MISC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Enable Watchdog timer and set the resolution to 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ~SP5100_PM_WATCHDOG_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SP5100_PM_WATCHDOG_SECOND_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case efch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Set the Watchdog timer resolution to 1 sec and enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ~EFCH_PM_WATCHDOG_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) EFCH_PM_DECODEEN_SECOND_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static u32 sp5100_tco_read_pm_reg32(u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = 3; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int sp5100_tco_setupdevice(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 mmio_addr = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Request the IO ports used by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(dev, "I/O address 0x%04x already in use\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SP5100_IO_PM_INDEX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Determine type of southbridge chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) switch (tco->tco_reg_layout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case sp5100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_name = SP5100_DEVNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0xfffffff8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case sb800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_name = SB800_DEVNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0xfffffff8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case efch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_name = SB800_DEVNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * region, it also enables the watchdog itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (boot_cpu_data.x86 == 0x17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) EFCH_PM_DECODEEN_WDT_TMREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (val & EFCH_PM_DECODEEN_WDT_TMREN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mmio_addr = EFCH_PM_WDT_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Check MMIO address conflict */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!mmio_addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (mmio_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_dbg(dev, "MMIO address 0x%08x already in use\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mmio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) switch (tco->tco_reg_layout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case sp5100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Secondly, Find the watchdog timer MMIO address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * from SBResource_MMIO register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pci_read_config_dword(sp5100_tco_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SP5100_SB_RESOURCE_MMIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) &mmio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SB800_ACPI_MMIO_SEL)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SB800_ACPI_MMIO_DECODE_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto unreg_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mmio_addr &= ~0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case sb800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mmio_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SB800_ACPI_MMIO_SEL)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SB800_ACPI_MMIO_DECODE_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) goto unreg_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mmio_addr &= ~0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case efch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) goto unreg_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) EFCH_PM_ACPI_MMIO_WDT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mmio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!devm_request_mem_region(dev, mmio_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SP5100_WDT_MEM_MAP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(dev, "MMIO address 0x%08x already in use\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mmio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) goto unreg_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!tco->tcobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_err(dev, "failed to get tcobase address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto unreg_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Setup the watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tco_timer_enable(tco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) val = readl(SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (val & SP5100_WDT_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(dev, "Watchdog hardware is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) goto unreg_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Save WatchDogFired status, because WatchDogFired flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * cleared here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (val & SP5100_WDT_FIRED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) wdd->bootstatus = WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Set watchdog action to reset the system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) val &= ~SP5100_WDT_ACTION_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel(val, SP5100_WDT_CONTROL(tco->tcobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Set a reasonable heartbeat before we stop the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tco_timer_set_timeout(wdd, wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * Stop the TCO before we change anything so we don't race with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * a zeroed timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) tco_timer_stop(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unreg_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct watchdog_info sp5100_tco_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .identity = "SP5100 TCO timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct watchdog_ops sp5100_tco_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .start = tco_timer_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .stop = tco_timer_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .ping = tco_timer_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .set_timeout = tco_timer_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int sp5100_tco_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct sp5100_tco *tco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!tco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) wdd = &tco->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) wdd->info = &sp5100_tco_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) wdd->ops = &sp5100_tco_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) wdd->timeout = WATCHDOG_HEARTBEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) wdd->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) wdd->max_timeout = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) watchdog_init_timeout(wdd, heartbeat, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) watchdog_set_nowayout(wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) watchdog_stop_on_reboot(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) watchdog_stop_on_unregister(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) watchdog_set_drvdata(wdd, tco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = sp5100_tco_setupdevice(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = devm_watchdog_register_device(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Show module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) wdd->timeout, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct platform_driver sp5100_tco_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .probe = sp5100_tco_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .name = TCO_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Data for PCI driver interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * This data only exists for exporting the supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * PCI ids via MODULE_DEVICE_TABLE. We do not actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * register a pci_driver, because someone else might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * want to register another driver on the same PCI id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct pci_device_id sp5100_tco_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 0, }, /* End of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int __init sp5100_tco_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct pci_dev *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Match the PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) for_each_pci_dev(dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sp5100_tco_pci = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!sp5100_tco_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) err = platform_driver_register(&sp5100_tco_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) sp5100_tco_platform_device =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (IS_ERR(sp5100_tco_platform_device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) err = PTR_ERR(sp5100_tco_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto unreg_platform_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unreg_platform_driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) platform_driver_unregister(&sp5100_tco_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void __exit sp5100_tco_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) platform_device_unregister(sp5100_tco_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) platform_driver_unregister(&sp5100_tco_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) module_init(sp5100_tco_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) module_exit(sp5100_tco_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MODULE_AUTHOR("Priyanka Gupta");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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