^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sl28cpld watchdog driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2020 Kontron Europe GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Watchdog timer block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WDT_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WDT_CTRL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WDT_CTRL_LOCK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WDT_CTRL_ASSERT_SYS_RESET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WDT_CTRL_ASSERT_WDT_TIMEOUT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WDT_TIMEOUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WDT_KICK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WDT_KICK_VALUE 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WDT_COUNT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WDT_DEFAULT_TIMEOUT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param(timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(timeout, "Initial watchdog timeout in seconds");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct sl28cpld_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool assert_wdt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int sl28cpld_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return regmap_write(wdt->regmap, wdt->offset + WDT_KICK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) WDT_KICK_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int sl28cpld_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val = WDT_CTRL_EN | WDT_CTRL_ASSERT_SYS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (wdt->assert_wdt_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) val |= WDT_CTRL_ASSERT_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (nowayout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val |= WDT_CTRL_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return regmap_update_bits(wdt->regmap, wdt->offset + WDT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int sl28cpld_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return regmap_update_bits(wdt->regmap, wdt->offset + WDT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) WDT_CTRL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static unsigned int sl28cpld_wdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = regmap_read(wdt->regmap, wdt->offset + WDT_COUNT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int sl28cpld_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = regmap_write(wdt->regmap, wdt->offset + WDT_TIMEOUT, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct watchdog_info sl28cpld_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .identity = "sl28cpld watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct watchdog_ops sl28cpld_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .start = sl28cpld_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .stop = sl28cpld_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .ping = sl28cpld_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .set_timeout = sl28cpld_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .get_timeleft = sl28cpld_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int sl28cpld_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct sl28cpld_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!pdev->dev.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) wdt->regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!wdt->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = device_property_read_u32(&pdev->dev, "reg", &wdt->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) wdt->assert_wdt_timeout = device_property_read_bool(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "kontron,assert-wdt-timeout-pin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* initialize struct watchdog_device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) wdd = &wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) wdd->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) wdd->info = &sl28cpld_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) wdd->ops = &sl28cpld_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) wdd->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) wdd->max_timeout = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) watchdog_set_drvdata(wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) watchdog_stop_on_reboot(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Read the status early, in case of an error, we haven't modified the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = regmap_read(wdt->regmap, wdt->offset + WDT_CTRL, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Initial timeout value, may be overwritten by device tree or module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * parmeter in watchdog_init_timeout().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Reading a zero here means that either the hardware has a default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * value of zero (which is very unlikely and definitely a hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * bug) or the bootloader set it to zero. In any case, we handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * this case gracefully and set out own timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = regmap_read(wdt->regmap, wdt->offset + WDT_TIMEOUT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) wdd->timeout = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) wdd->timeout = WDT_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) watchdog_init_timeout(wdd, timeout, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sl28cpld_wdt_set_timeout(wdd, wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* if the watchdog is locked, we set nowayout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (status & WDT_CTRL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) nowayout = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) watchdog_set_nowayout(wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * If watchdog is already running, keep it enabled, but make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * sure its mode is set correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (status & WDT_CTRL_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sl28cpld_wdt_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) set_bit(WDOG_HW_RUNNING, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = devm_watchdog_register_device(&pdev->dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(&pdev->dev, "failed to register watchdog device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_info(&pdev->dev, "initial timeout %d sec%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) wdd->timeout, nowayout ? ", nowayout" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct of_device_id sl28cpld_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .compatible = "kontron,sl28cpld-wdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_DEVICE_TABLE(of, sl28cpld_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct platform_driver sl28cpld_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .probe = sl28cpld_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "sl28cpld-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .of_match_table = sl28cpld_wdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) module_platform_driver(sl28cpld_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MODULE_DESCRIPTION("sl28cpld Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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