^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Watchdog driver for CSR SiRFprimaII and SiRFatlasVI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLOCK_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIRFSOC_TIMER_COUNTER_LO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIRFSOC_TIMER_MATCH_0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIRFSOC_TIMER_INT_EN 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIRFSOC_TIMER_LATCH 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SIRFSOC_TIMER_LATCHED_LO 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIRFSOC_TIMER_WDT_INDEX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIRFSOC_WDT_MIN_TIMEOUT 30 /* 30 secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIRFSOC_WDT_MAX_TIMEOUT (10 * 60) /* 10 mins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIRFSOC_WDT_DEFAULT_TIMEOUT 30 /* 30 secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) module_param(timeout, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void __iomem *sirfsoc_wdt_base(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return (void __iomem __force *)watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static unsigned int sirfsoc_wdt_gettimeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 counter, match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) wdt_base = sirfsoc_wdt_base(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) counter = readl(wdt_base + SIRFSOC_TIMER_COUNTER_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) match = readl(wdt_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) time_left = match - counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return time_left / CLOCK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int sirfsoc_wdt_updatetimeout(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 counter, timeout_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) timeout_ticks = wdd->timeout * CLOCK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) wdt_base = sirfsoc_wdt_base(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Enable the latch before reading the LATCH_LO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(1, wdt_base + SIRFSOC_TIMER_LATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Set the TO value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) counter = readl(wdt_base + SIRFSOC_TIMER_LATCHED_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) counter += timeout_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(counter, wdt_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int sirfsoc_wdt_enable(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *wdt_base = sirfsoc_wdt_base(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sirfsoc_wdt_updatetimeout(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * NOTE: If interrupt is not enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * then WD-Reset doesn't get generated at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) | (1 << SIRFSOC_TIMER_WDT_INDEX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) wdt_base + SIRFSOC_TIMER_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(1, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int sirfsoc_wdt_disable(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __iomem *wdt_base = sirfsoc_wdt_base(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(0, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) & (~(1 << SIRFSOC_TIMER_WDT_INDEX)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) wdt_base + SIRFSOC_TIMER_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int sirfsoc_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) wdd->timeout = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sirfsoc_wdt_updatetimeout(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct watchdog_info sirfsoc_wdt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .options = OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .firmware_version = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .identity = "SiRFSOC Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct watchdog_ops sirfsoc_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .start = sirfsoc_wdt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .stop = sirfsoc_wdt_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .get_timeleft = sirfsoc_wdt_gettimeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .ping = sirfsoc_wdt_updatetimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .set_timeout = sirfsoc_wdt_settimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct watchdog_device sirfsoc_wdd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .info = &sirfsoc_wdt_ident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .ops = &sirfsoc_wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .min_timeout = SIRFSOC_WDT_MIN_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .max_timeout = SIRFSOC_WDT_MAX_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int sirfsoc_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) watchdog_set_drvdata(&sirfsoc_wdd, (__force void *)base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) watchdog_init_timeout(&sirfsoc_wdd, timeout, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) watchdog_set_nowayout(&sirfsoc_wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sirfsoc_wdd.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) watchdog_stop_on_reboot(&sirfsoc_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) watchdog_stop_on_unregister(&sirfsoc_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = devm_watchdog_register_device(dev, &sirfsoc_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) platform_set_drvdata(pdev, &sirfsoc_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int sirfsoc_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int sirfsoc_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct watchdog_device *wdd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * NOTE: Since timer controller registers settings are saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * and restored back by the timer-prima2.c, so we need not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * update WD settings except refreshing timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sirfsoc_wdt_updatetimeout(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static SIMPLE_DEV_PM_OPS(sirfsoc_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) sirfsoc_wdt_suspend, sirfsoc_wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct of_device_id sirfsoc_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .compatible = "sirf,prima2-tick"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_DEVICE_TABLE(of, sirfsoc_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct platform_driver sirfsoc_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "sirfsoc-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .pm = &sirfsoc_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .of_match_table = sirfsoc_wdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .probe = sirfsoc_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) module_platform_driver(sirfsoc_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_DESCRIPTION("SiRF SoC watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_ALIAS("platform:sirfsoc-wdt");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags