^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SBSA(Server Base System Architecture) Generic Watchdog driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Fu Wei <fu.wei@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Al Stone <al.stone@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Timur Tabi <timur@codeaurora.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * ARM SBSA Generic Watchdog has two stage timeouts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the first signal (WS0) is for alerting the system by interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * the second one (WS1) is a real hardware reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * More details about the hardware specification of this device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ARM DEN0029B - Server Base System Architecture (SBSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * or a two stages watchdog, it's set up by the module parameter "action".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * In the single stage mode, when the timeout is reached, your system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * will be reset by WS1. The first signal (WS0) is ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * In the two stages mode, when the timeout is reached, the first signal (WS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * will trigger panic. If the system is getting into trouble and cannot be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * by panic or restart properly by the kdump kernel(if supported), then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * second stage (as long as the first stage) will be reached, system will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * reset by WS1. This function can help administrator to backup the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * context info by panic console output or kdump.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SBSA GWDT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * if action is 1 (the two stages mode):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * |--------WOR-------WS0--------WOR-------WS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * |----timeout-----(panic)----timeout-----reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * if action is 0 (the single stage mode):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * |------WOR-----WS0(ignored)-----WOR------WS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * |--------------timeout-------------------reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Note: Since this watchdog timer has two stages, and each stage is determined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * stages mode, the timeout is WOR. The maximum timeout in the two stages mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * is half of that in the single stage mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/arch_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRV_NAME "sbsa-gwdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WATCHDOG_NAME "SBSA Generic Watchdog"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* SBSA Generic Watchdog register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* refresh frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SBSA_GWDT_WRR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* control frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SBSA_GWDT_WCS 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SBSA_GWDT_WOR 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SBSA_GWDT_WCV 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* refresh/control frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SBSA_GWDT_W_IIDR 0xfcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SBSA_GWDT_IDR 0xfd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Watchdog Control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SBSA_GWDT_WCS_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SBSA_GWDT_WCS_WS0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SBSA_GWDT_WCS_WS1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * struct sbsa_gwdt - Internal representation of the SBSA GWDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @wdd: kernel watchdog_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @clk: store the System Counter clock frequency, in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @refresh_base: Virtual address of the watchdog refresh frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @control_base: Virtual address of the watchdog control frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct sbsa_gwdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *refresh_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *control_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEFAULT_TIMEOUT 10 /* seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) module_param(timeout, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_PARM_DESC(timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "Watchdog timeout in seconds. (>=0, default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __MODULE_STRING(DEFAULT_TIMEOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * action refers to action taken when watchdog gets WS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 0 = skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 1 = panic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * defaults to skip (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) module_param(action, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "0 = skip(*) 1 = panic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) module_param(nowayout, bool, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * watchdog operation functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(gwdt->clk * timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) gwdt->control_base + SBSA_GWDT_WOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * In the single stage mode, The first signal (WS0) is ignored,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * the timeout is (WOR * 2), so the WOR should be configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * to half value of timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(gwdt->clk / 2 * timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) gwdt->control_base + SBSA_GWDT_WOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 timeleft = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * In the single stage mode, if WS0 is deasserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * (watchdog is in the first stage),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * timeleft = WOR + (WCV - system counter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!action &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) arch_timer_read_counter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) do_div(timeleft, gwdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Writing WRR for an explicit watchdog refresh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * You can write anyting (like 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int sbsa_gwdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* writing WCS will cause an explicit watchdog refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int sbsa_gwdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Simply write 0 to WCS to clean WCS_EN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(0, gwdt->control_base + SBSA_GWDT_WCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) panic(WATCHDOG_NAME " timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct watchdog_info sbsa_gwdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .identity = WATCHDOG_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .options = WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) WDIOF_CARDRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct watchdog_ops sbsa_gwdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .start = sbsa_gwdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .stop = sbsa_gwdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .ping = sbsa_gwdt_keepalive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .set_timeout = sbsa_gwdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .get_timeleft = sbsa_gwdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int sbsa_gwdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void __iomem *rf_base, *cf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct sbsa_gwdt *gwdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!gwdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) platform_set_drvdata(pdev, gwdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cf_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (IS_ERR(cf_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return PTR_ERR(cf_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rf_base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(rf_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PTR_ERR(rf_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Get the frequency of system counter from the cp15 interface of ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Generic timer. We don't need to check it, because if it returns "0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * system would panic in very early stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) gwdt->clk = arch_timer_get_cntfrq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gwdt->refresh_base = rf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) gwdt->control_base = cf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) wdd = &gwdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) wdd->info = &sbsa_gwdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) wdd->ops = &sbsa_gwdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) wdd->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) wdd->timeout = DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) watchdog_set_drvdata(wdd, gwdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) watchdog_set_nowayout(wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) status = readl(cf_base + SBSA_GWDT_WCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (status & SBSA_GWDT_WCS_WS1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_warn(dev, "System reset by WDT.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) wdd->bootstatus |= WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (status & SBSA_GWDT_WCS_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) set_bit(WDOG_HW_RUNNING, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) action = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_warn(dev, "unable to get ws0 interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * In case there is a pending ws0 interrupt, just ping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * the watchdog before registering the interrupt routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(0, rf_base + SBSA_GWDT_WRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pdev->name, gwdt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) action = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_warn(dev, "unable to request IRQ %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_warn(dev, "falling back to single stage mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * In the single stage mode, The first signal (WS0) is ignored,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * the timeout is (WOR * 2), so the maximum timeout should be doubled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) wdd->max_hw_heartbeat_ms *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) watchdog_init_timeout(wdd, timeout, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Update timeout to WOR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Because of the explicit watchdog refresh mechanism,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * it's also a ping, if watchdog is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) sbsa_gwdt_set_timeout(wdd, wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) watchdog_stop_on_reboot(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = devm_watchdog_register_device(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) wdd->timeout, gwdt->clk, action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Disable watchdog if it is active during suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (watchdog_active(&gwdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) sbsa_gwdt_stop(&gwdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Enable watchdog if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (watchdog_active(&gwdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) sbsa_gwdt_start(&gwdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct of_device_id sbsa_gwdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { .compatible = "arm,sbsa-gwdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { .name = DRV_NAME, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct platform_driver sbsa_gwdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .pm = &sbsa_gwdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .of_match_table = sbsa_gwdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .probe = sbsa_gwdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .id_table = sbsa_gwdt_pdev_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) module_platform_driver(sbsa_gwdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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