^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Atmel SAMA5D4 Watchdog Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-2019 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "at91sam9_wdt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* minimum and maximum watchdog timeout, in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MIN_WDT_TIMEOUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_WDT_TIMEOUT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct sama5d4_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long last_ping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bool need_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool sam9x60_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int wdt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(wdt_timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(wdt_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "Watchdog timeout in seconds. (default = "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define wdt_read(wdt, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) readl_relaxed((wdt)->reg_base + (field))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* 4 slow clock periods is 4/32768 = 122.07µs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WDT_DELAY usecs_to_jiffies(123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * WDT_CR and WDT_MR must not be modified within three slow clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * periods following a restart of the watchdog performed by a write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * access in WDT_CR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) usleep_range(30, 125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel_relaxed(val, wdt->reg_base + field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) wdt->last_ping = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) udelay(123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel_relaxed(val, wdt->reg_base + field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) wdt->last_ping = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int sama5d4_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (wdt->sam9x60_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) wdt->mr &= ~AT91_SAM9X60_WDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) wdt->mr &= ~AT91_WDT_WDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) wdt_write(wdt, AT91_WDT_MR, wdt->mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int sama5d4_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (wdt->sam9x60_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) wdt->mr |= AT91_SAM9X60_WDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) wdt->mr |= AT91_WDT_WDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) wdt_write(wdt, AT91_WDT_MR, wdt->mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int sama5d4_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 value = WDT_SEC2TICKS(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (wdt->sam9x60_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) wdt_write(wdt, AT91_SAM9X60_WLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) AT91_SAM9X60_SET_COUNTER(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) wdt->mr &= ~AT91_WDT_WDV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) wdt->mr |= AT91_WDT_SET_WDV(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * setting the WDDIS bit, and while it is set, the fields WDV and WDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * must not be modified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * If the watchdog is enabled, then the timeout can be updated. Else,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * wait that the user enables it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (wdt_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct watchdog_info sama5d4_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .identity = "Atmel SAMA5D4 Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct watchdog_ops sama5d4_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .start = sama5d4_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .stop = sama5d4_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .ping = sama5d4_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .set_timeout = sama5d4_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (wdt->sam9x60_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg = wdt_read(wdt, AT91_SAM9X60_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg = wdt_read(wdt, AT91_WDT_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pr_crit("Atmel Watchdog Software Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) emergency_restart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pr_crit("Reboot didn't succeed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const char *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (wdt->sam9x60_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) wdt->mr = AT91_SAM9X60_WDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) wdt->mr = AT91_WDT_WDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) !strcmp(tmp, "software"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wdt->need_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (of_property_read_bool(np, "atmel,idle-halt"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) wdt->mr |= AT91_WDT_WDIDLEHLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (of_property_read_bool(np, "atmel,dbg-halt"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) wdt->mr |= AT91_WDT_WDDBGHLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val = WDT_SEC2TICKS(WDT_DEFAULT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * When booting and resuming, the bootloader may have changed the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * watchdog configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * If the watchdog is already running, we can safely update it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Else, we have to disable it properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!wdt_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = wdt_read(wdt, AT91_WDT_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) wdt_write_nosleep(wdt, AT91_WDT_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg | AT91_SAM9X60_WDDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) else if (!wdt->sam9x60_support &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (!(reg & AT91_WDT_WDDIS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) wdt_write_nosleep(wdt, AT91_WDT_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg | AT91_WDT_WDDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (wdt->sam9x60_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (wdt->need_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) wdt->ir = AT91_SAM9X60_PERINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) wdt->mr |= AT91_SAM9X60_PERIODRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) wdt->mr |= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) wdt->mr |= AT91_WDT_SET_WDV(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (wdt->need_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) wdt->mr |= AT91_WDT_WDFIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) wdt->mr |= AT91_WDT_WDRSTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int sama5d4_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct sama5d4_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) wdd = &wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) wdd->timeout = WDT_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) wdd->info = &sama5d4_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) wdd->ops = &sama5d4_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) wdd->min_timeout = MIN_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) wdd->max_timeout = MAX_WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wdt->last_ping = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) wdt->sam9x60_support = of_device_is_compatible(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "microchip,sam9x60-wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) watchdog_set_drvdata(wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) wdt->reg_base = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = of_sama5d4_wdt_init(dev->of_node, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (wdt->need_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) irq = irq_of_parse_and_map(dev->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_warn(dev, "failed to get IRQ from DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) wdt->need_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (wdt->need_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) IRQF_SHARED | IRQF_IRQPOLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) IRQF_NO_SUSPEND, pdev->name, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(dev, "cannot register interrupt handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) watchdog_init_timeout(wdd, wdt_timeout, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = sama5d4_wdt_init(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) watchdog_set_nowayout(wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) watchdog_stop_on_unregister(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = devm_watchdog_register_device(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) wdd->timeout, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct of_device_id sama5d4_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .compatible = "atmel,sama5d4-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .compatible = "microchip,sam9x60-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int sama5d4_wdt_suspend_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) sama5d4_wdt_stop(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int sama5d4_wdt_resume_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * FIXME: writing MR also pings the watchdog which may not be desired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * This should only be done when the registers are lost on suspend but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * there is no way to get this information right now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sama5d4_wdt_init(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sama5d4_wdt_start(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct dev_pm_ops sama5d4_wdt_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SET_LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sama5d4_wdt_resume_early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct platform_driver sama5d4_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .probe = sama5d4_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .name = "sama5d4_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .pm = &sama5d4_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .of_match_table = sama5d4_wdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) module_platform_driver(sama5d4_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_AUTHOR("Atmel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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