^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2004 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * S3C2410 Watchdog Timer Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on, softdog.c by Alan Cox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2410_WTCON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2410_WTDAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2410_WTCNT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2410_WTCLRINT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C2410_WTCNT_MAXCNT 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2410_WTCON_RSTEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2410_WTCON_INTEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2410_WTCON_ENABLE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C2410_WTCON_DIV16 (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2410_WTCON_DIV32 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_WTCON_DIV64 (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C2410_WTCON_DIV128 (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2410_WTCON_MAXDIV 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C2410_WTCON_PRESCALE_MAX 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C2410_WATCHDOG_ATBOOT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C2410_WATCHDOG_DEFAULT_TIME (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QUIRK_HAS_PMU_CONFIG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QUIRK_HAS_RST_STAT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QUIRK_HAS_WTCLRINT_REG (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* These quirks require that we have a PMU register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) QUIRK_HAS_RST_STAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int tmr_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int soft_noboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) module_param(tmr_margin, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) module_param(tmr_atboot, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) module_param(soft_noboot, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_PARM_DESC(tmr_atboot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "Watchdog is started at boot time if set to 1, default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * struct s3c2410_wdt_variant - Per-variant config data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @disable_reg: Offset in pmureg for the register that disables the watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * timer reset functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * timer reset functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @mask_bit: Bit number for the watchdog timer in the disable register and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * mask reset register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @quirks: A bitfield of quirks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct s3c2410_wdt_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int mask_reset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int mask_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int rst_stat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int rst_stat_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct s3c2410_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long wtcon_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long wtdat_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct watchdog_device wdt_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct notifier_block freq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct s3c2410_wdt_variant *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regmap *pmureg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .quirks = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .quirks = QUIRK_HAS_WTCLRINT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mask_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .rst_stat_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) | QUIRK_HAS_WTCLRINT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .mask_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .rst_stat_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) | QUIRK_HAS_WTCLRINT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct s3c2410_wdt_variant drv_data_exynos7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mask_bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .rst_stat_bit = 23, /* A57 WDTRESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) | QUIRK_HAS_WTCLRINT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct of_device_id s3c2410_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .compatible = "samsung,s3c2410-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .data = &drv_data_s3c2410 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .compatible = "samsung,s3c6410-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .data = &drv_data_s3c6410 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .compatible = "samsung,exynos5250-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .data = &drv_data_exynos5250 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .compatible = "samsung,exynos5420-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .data = &drv_data_exynos5420 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .compatible = "samsung,exynos7-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .data = &drv_data_exynos7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct platform_device_id s3c2410_wdt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "s3c2410-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .driver_data = (unsigned long)&drv_data_s3c2410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long freq = clk_get_rate(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) / S3C2410_WTCON_MAXDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return container_of(nb, struct s3c2410_wdt, freq_transition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 mask_val = 1 << wdt->drv_data->mask_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* No need to do anything if no PMU CONFIG needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val = mask_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = regmap_update_bits(wdt->pmureg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) wdt->drv_data->disable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mask_val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = regmap_update_bits(wdt->pmureg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) wdt->drv_data->mask_reset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mask_val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) spin_lock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_unlock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long wtcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) wtcon = readl(wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(wtcon, wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int s3c2410wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spin_lock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __s3c2410wdt_stop(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) spin_unlock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int s3c2410wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long wtcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spin_lock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __s3c2410wdt_stop(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) wtcon = readl(wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (soft_noboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wtcon |= S3C2410_WTCON_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) wtcon &= ~S3C2410_WTCON_RSTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) wtcon &= ~S3C2410_WTCON_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) wtcon |= S3C2410_WTCON_RSTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) wdt->count, wtcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writel(wtcon, wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) spin_unlock(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long freq = clk_get_rate(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int divisor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long wtcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (timeout < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) freq = DIV_ROUND_UP(freq, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) count = timeout * freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) count, timeout, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* if the count is bigger than the watchdog register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) then work out what we need to do (and if) we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) actually make this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (count >= 0x10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) divisor = DIV_ROUND_UP(count, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (divisor > 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(wdt->dev, "timeout %d too big\n", timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) timeout, divisor, count, DIV_ROUND_UP(count, divisor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) count = DIV_ROUND_UP(count, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) wdt->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* update the pre-scaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) wtcon = readl(wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(count, wdt->reg_base + S3C2410_WTDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(wtcon, wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) wdd->timeout = (count * divisor) / freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) void __iomem *wdt_base = wdt->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* disable watchdog, to be safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel(0, wdt_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* put initial values into count and data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel(0x80, wdt_base + S3C2410_WTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) writel(0x80, wdt_base + S3C2410_WTDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* set the watchdog to go and reset... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) wdt_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* wait for reset to assert... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mdelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct watchdog_info s3c2410_wdt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .options = OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .firmware_version = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .identity = "S3C2410 Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct watchdog_ops s3c2410wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .start = s3c2410wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .stop = s3c2410wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .ping = s3c2410wdt_keepalive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .set_timeout = s3c2410wdt_set_heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .restart = s3c2410wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct watchdog_device s3c2410_wdd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .info = &s3c2410_wdt_ident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .ops = &s3c2410wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* interrupt handler code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct s3c2410_wdt *wdt = platform_get_drvdata(param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_info(wdt->dev, "watchdog timer expired (irq)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) s3c2410wdt_keepalive(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long val, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct s3c2410_wdt *wdt = freq_to_wdt(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!s3c2410wdt_is_running(wdt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (val == CPUFREQ_PRECHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* To ensure that over the change we don't cause the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * watchdog to trigger, we perform an keep-alive if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * the watchdog is running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) s3c2410wdt_keepalive(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } else if (val == CPUFREQ_POSTCHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) s3c2410wdt_stop(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) wdt->wdt_device.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) s3c2410wdt_start(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(wdt->dev, "cannot set new value for timeout %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) wdt->wdt_device.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return cpufreq_register_notifier(&wdt->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) cpufreq_unregister_notifier(&wdt->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int rst_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static inline const struct s3c2410_wdt_variant *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) s3c2410_get_wdt_drv_data(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const struct s3c2410_wdt_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) variant = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Device matched by platform_device_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) variant = (struct s3c2410_wdt_variant *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int s3c2410wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct s3c2410_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct resource *wdt_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int wtcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) wdt->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_lock_init(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) wdt->wdt_device = s3c2410_wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) wdt->drv_data = s3c2410_get_wdt_drv_data(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "samsung,syscon-phandle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(wdt->pmureg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_err(dev, "syscon regmap lookup failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return PTR_ERR(wdt->pmureg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (wdt_irq == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(dev, "no irq resource specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* get the memory region for the watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (IS_ERR(wdt->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = PTR_ERR(wdt->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) wdt->clock = devm_clk_get(dev, "watchdog");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (IS_ERR(wdt->clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(dev, "failed to find watchdog clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = PTR_ERR(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = clk_prepare_enable(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) wdt->wdt_device.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = s3c2410wdt_cpufreq_register(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(dev, "failed to register cpufreq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) watchdog_set_drvdata(&wdt->wdt_device, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* see if we can actually set the requested timer margin, and if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * not, try the default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) wdt->wdt_device.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) S3C2410_WATCHDOG_DEFAULT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (started == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "tmr_margin value out of range, default %d used\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) S3C2410_WATCHDOG_DEFAULT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_info(dev, "default timer value is out of range, cannot start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pdev->name, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_err(dev, "failed to install irq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto err_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) watchdog_set_nowayout(&wdt->wdt_device, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) watchdog_set_restart_priority(&wdt->wdt_device, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) wdt->wdt_device.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = watchdog_register_device(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto err_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) goto err_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (tmr_atboot && started == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_info(dev, "starting watchdog timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) s3c2410wdt_start(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } else if (!tmr_atboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* if we're not enabling the watchdog, then ensure it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * disabled if it has been left running from the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * or other source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) s3c2410wdt_stop(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* print out a statement of readiness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) wtcon = readl(wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) err_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) watchdog_unregister_device(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) err_cpufreq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) s3c2410wdt_cpufreq_deregister(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) clk_disable_unprepare(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int s3c2410wdt_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) watchdog_unregister_device(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) s3c2410wdt_cpufreq_deregister(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clk_disable_unprepare(wdt->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static void s3c2410wdt_shutdown(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) s3c2410wdt_mask_and_disable_reset(wdt, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) s3c2410wdt_stop(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int s3c2410wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Save watchdog state, and turn it off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Note that WTCNT doesn't need to be saved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) s3c2410wdt_stop(&wdt->wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int s3c2410wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Restore watchdog state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_info(dev, "watchdog %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) s3c2410wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static struct platform_driver s3c2410wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .probe = s3c2410wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .remove = s3c2410wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .shutdown = s3c2410wdt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .id_table = s3c2410_wdt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .name = "s3c2410-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .pm = &s3c2410wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .of_match_table = of_match_ptr(s3c2410_wdt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) module_platform_driver(s3c2410wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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