^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Watchdog driver for the K3 RTI module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) Copyright 2019-2020 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DEFAULT_HEARTBEAT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Max heartbeat is calculated at 32kHz source clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_HEARTBEAT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Timer register set definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTIDWDCTRL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTIDWDPRLD 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTIWDSTATUS 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTIWDKEY 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTIDWDCNTR 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTIWWDRXCTRL 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTIWWDSIZECTRL 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTIWWDRX_NMI 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTIWWDSIZE_50P 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTIWWDSIZE_25P 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTIWWDSIZE_12P5 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTIWWDSIZE_6P25 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTIWWDSIZE_3P125 0x500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WDENABLE_KEY 0xa98559da
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WDKEY_SEQ0 0xe51a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WDKEY_SEQ1 0xa35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WDT_PRELOAD_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WDT_PRELOAD_MAX 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DWDST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int heartbeat = DEFAULT_HEARTBEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * struct to hold data for each WDT device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @base - base io address of WD device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @freq - source clock frequency of WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @wdd - hold watchdog device as is in WDT core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct rti_wdt_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int rti_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 timer_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* set timeout period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) timer_margin = (u64)wdd->timeout * wdt->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) timer_margin >>= WDT_PRELOAD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (timer_margin > WDT_PRELOAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) timer_margin = WDT_PRELOAD_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * RTI only supports a windowed mode, where the watchdog can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * be petted during the open window; not too early or not too late.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * The HW configuration options only allow for the open window size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * to be 50% or less than that; we obviouly want to configure the open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * window as large as possible so we select the 50% option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) wdd->min_hw_heartbeat_ms = 500 * wdd->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Generate NMI when wdt expires */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel_relaxed(RTIWWDRX_NMI, wdt->base + RTIWWDRXCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Open window size 50%; this is the largest window size available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel_relaxed(RTIWWDSIZE_50P, wdt->base + RTIWWDSIZECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) readl_relaxed(wdt->base + RTIWWDSIZECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* enable watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(WDENABLE_KEY, wdt->base + RTIDWDCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int rti_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* put watchdog in service state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel_relaxed(WDKEY_SEQ0, wdt->base + RTIWDKEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* put watchdog in active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel_relaxed(WDKEY_SEQ1, wdt->base + RTIWDKEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int rti_wdt_setup_hw_hb(struct watchdog_device *wdd, u32 wsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * RTI only supports a windowed mode, where the watchdog can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * be petted during the open window; not too early or not too late.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * The HW configuration options only allow for the open window size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * to be 50% or less than that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) switch (wsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case RTIWWDSIZE_50P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* 50% open window => 50% min heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) wdd->min_hw_heartbeat_ms = 500 * heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case RTIWWDSIZE_25P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 25% open window => 75% min heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wdd->min_hw_heartbeat_ms = 750 * heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case RTIWWDSIZE_12P5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 12.5% open window => 87.5% min heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) wdd->min_hw_heartbeat_ms = 875 * heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case RTIWWDSIZE_6P25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* 6.5% open window => 93.5% min heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) wdd->min_hw_heartbeat_ms = 935 * heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case RTIWWDSIZE_3P125:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* 3.125% open window => 96.9% min heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) wdd->min_hw_heartbeat_ms = 969 * heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static unsigned int rti_wdt_get_timeleft_ms(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u64 timer_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* if timeout has occurred then return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = readl_relaxed(wdt->base + RTIWDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (val & DWDST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) timer_counter = readl_relaxed(wdt->base + RTIDWDCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) timer_counter *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) do_div(timer_counter, wdt->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return timer_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static unsigned int rti_wdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return rti_wdt_get_timeleft_ms(wdd) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct watchdog_info rti_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .options = WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .identity = "K3 RTI Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct watchdog_ops rti_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .start = rti_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .ping = rti_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .get_timeleft = rti_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int rti_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct resource *wdt_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct rti_wdt_device *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 last_ping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk = clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) wdt->freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!wdt->freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(dev, "Failed to get fck rate.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * If watchdog is running at 32k clock, it is not accurate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Adjust frequency down in this case so that we don't pet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * the watchdog too often.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (wdt->freq < 32768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) wdt->freq = wdt->freq * 9 / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return dev_err_probe(dev, ret, "runtime pm failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) wdd = &wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) wdd->info = &rti_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) wdd->ops = &rti_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) wdd->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) wdd->max_hw_heartbeat_ms = (WDT_PRELOAD_MAX << WDT_PRELOAD_SHIFT) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) wdt->freq * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) watchdog_set_drvdata(wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) watchdog_set_nowayout(wdd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) watchdog_set_restart_priority(wdd, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) wdt->base = devm_ioremap_resource(dev, wdt_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (IS_ERR(wdt->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = PTR_ERR(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (readl(wdt->base + RTIDWDCTRL) == WDENABLE_KEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 time_left_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u64 heartbeat_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) set_bit(WDOG_HW_RUNNING, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) time_left_ms = rti_wdt_get_timeleft_ms(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) heartbeat_ms = readl(wdt->base + RTIDWDPRLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) heartbeat_ms <<= WDT_PRELOAD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) heartbeat_ms *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) do_div(heartbeat_ms, wdt->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (heartbeat_ms != heartbeat * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_warn(dev, "watchdog already running, ignoring heartbeat config!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) heartbeat = heartbeat_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) heartbeat /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) wsize = readl(wdt->base + RTIWWDSIZECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = rti_wdt_setup_hw_hb(wdd, wsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(dev, "bad window size.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) last_ping = heartbeat_ms - time_left_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (time_left_ms > heartbeat_ms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_warn(dev, "time_left > heartbeat? Assuming last ping just before now.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) last_ping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) watchdog_init_timeout(wdd, heartbeat, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = watchdog_register_device(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev, "cannot register watchdog device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (last_ping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) watchdog_set_last_hw_keepalive(wdd, last_ping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) err_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int rti_wdt_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct rti_wdt_device *wdt = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) watchdog_unregister_device(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct of_device_id rti_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { .compatible = "ti,j7-rti-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_DEVICE_TABLE(of, rti_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct platform_driver rti_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "rti-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .of_match_table = rti_wdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .probe = rti_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .remove = rti_wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) module_platform_driver(rti_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_AUTHOR("Tero Kristo <t-kristo@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_DESCRIPTION("K3 RTI Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_PARM_DESC(heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "Watchdog heartbeat period in seconds from 1 to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) __MODULE_STRING(MAX_HEARTBEAT) ", default "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __MODULE_STRING(DEFAULT_HEARTBEAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_ALIAS("platform:rti-wdt");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags