^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver was based on: drivers/watchdog/softdog.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SYSC_RSTSTAT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WDT_RST_CAUSE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RALINK_WDT_TIMEOUT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RALINK_WDT_PRESCALE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TIMER_REG_TMR1LOAD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIMER_REG_TMR1CTL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TMRSTAT_TMR1RST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TMR1CTL_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TMR1CTL_MODE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TMR1CTL_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TMR1CTL_MODE_FREE_RUNNING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TMR1CTL_MODE_PERIODIC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TMR1CTL_MODE_TIMEOUT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TMR1CTL_MODE_WDT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TMR1CTL_PRESCALE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TMR1CTL_PRESCALE_65536 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct clk *rt288x_wdt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static unsigned long rt288x_wdt_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void __iomem *rt288x_wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct reset_control *rt288x_wdt_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline void rt_wdt_w32(unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) iowrite32(val, rt288x_wdt_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline u32 rt_wdt_r32(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return ioread32(rt288x_wdt_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int rt288x_wdt_ping(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int rt288x_wdt_start(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) t = rt_wdt_r32(TIMER_REG_TMR1CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) TMR1CTL_PRESCALE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) TMR1CTL_PRESCALE_65536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) rt_wdt_w32(TIMER_REG_TMR1CTL, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rt288x_wdt_ping(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) t = rt_wdt_r32(TIMER_REG_TMR1CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) t |= TMR1CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) rt_wdt_w32(TIMER_REG_TMR1CTL, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int rt288x_wdt_stop(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) rt288x_wdt_ping(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) t = rt_wdt_r32(TIMER_REG_TMR1CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) t &= ~TMR1CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) rt_wdt_w32(TIMER_REG_TMR1CTL, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) w->timeout = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rt288x_wdt_ping(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int rt288x_wdt_bootcause(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct watchdog_info rt288x_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .identity = "Ralink Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct watchdog_ops rt288x_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .start = rt288x_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .stop = rt288x_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .ping = rt288x_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .set_timeout = rt288x_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct watchdog_device rt288x_wdt_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .info = &rt288x_wdt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .ops = &rt288x_wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .min_timeout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int rt288x_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rt288x_wdt_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (IS_ERR(rt288x_wdt_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return PTR_ERR(rt288x_wdt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rt288x_wdt_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (IS_ERR(rt288x_wdt_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return PTR_ERR(rt288x_wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rt288x_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!IS_ERR(rt288x_wdt_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reset_control_deassert(rt288x_wdt_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rt288x_wdt_dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) watchdog_init_timeout(&rt288x_wdt_dev, rt288x_wdt_dev.max_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) watchdog_stop_on_reboot(&rt288x_wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = devm_watchdog_register_device(dev, &rt288x_wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_info(dev, "Initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct of_device_id rt288x_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .compatible = "ralink,rt2880-wdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct platform_driver rt288x_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .probe = rt288x_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .of_match_table = rt288x_wdt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) module_platform_driver(rt288x_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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