^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum wdt_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) WDT_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) WDT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) WDT_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) WDT_BARK_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) WDT_BITE_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QCOM_WDT_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const u32 reg_offset_data_apcs_tmr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [WDT_RST] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [WDT_EN] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [WDT_STS] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [WDT_BARK_TIME] = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [WDT_BITE_TIME] = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const u32 reg_offset_data_kpss[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [WDT_RST] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [WDT_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [WDT_STS] = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [WDT_BARK_TIME] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [WDT_BITE_TIME] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct qcom_wdt_match_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const u32 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool pretimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct qcom_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const u32 *layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return wdt->base + wdt->layout[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return container_of(wdd, struct qcom_wdt, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static irqreturn_t qcom_wdt_isr(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct watchdog_device *wdd = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) watchdog_notify_pretimeout(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int qcom_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct qcom_wdt *wdt = to_qcom_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int bark = wdd->timeout - wdd->pretimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel(0, wdt_addr(wdt, WDT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel(1, wdt_addr(wdt, WDT_RST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int qcom_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct qcom_wdt *wdt = to_qcom_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(0, wdt_addr(wdt, WDT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int qcom_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct qcom_wdt *wdt = to_qcom_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(1, wdt_addr(wdt, WDT_RST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return qcom_wdt_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) wdd->pretimeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return qcom_wdt_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct qcom_wdt *wdt = to_qcom_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Trigger watchdog bite:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Setup BITE_TIME to be 128ms, and enable WDT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) timeout = 128 * wdt->rate / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(0, wdt_addr(wdt, WDT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(1, wdt_addr(wdt, WDT_RST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Actually make sure the above sequence hits hardware before sleeping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mdelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct watchdog_ops qcom_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .start = qcom_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .stop = qcom_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .ping = qcom_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .set_timeout = qcom_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .set_pretimeout = qcom_wdt_set_pretimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .restart = qcom_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct watchdog_info qcom_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .options = WDIOF_KEEPALIVEPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) | WDIOF_MAGICCLOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) | WDIOF_SETTIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) | WDIOF_CARDRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .identity = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct watchdog_info qcom_wdt_pt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .options = WDIOF_KEEPALIVEPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) | WDIOF_MAGICCLOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) | WDIOF_SETTIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) | WDIOF_PRETIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) | WDIOF_CARDRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .identity = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void qcom_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct qcom_wdt_match_data match_data_apcs_tmr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .offset = reg_offset_data_apcs_tmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .pretimeout = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct qcom_wdt_match_data match_data_kpss = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .offset = reg_offset_data_kpss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .pretimeout = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int qcom_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct qcom_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const struct qcom_wdt_match_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 percpu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(dev, "Unsupported QCOM WDT module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* We use CPU0's DGT for the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) percpu_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) res->start += percpu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) res->end += percpu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) wdt->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (IS_ERR(wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return PTR_ERR(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(dev, "failed to get input clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(dev, "failed to setup clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * We use the clock rate to calculate the max timeout, so ensure it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * not zero to avoid a divide-by-zero exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * that it would bite before a second elapses it's usefulness is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * limited. Bail if this is the case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) wdt->rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (wdt->rate == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) wdt->rate > 0x10000000U) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_err(dev, "invalid clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* check if there is pretimeout support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) irq = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (data->pretimeout && irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "wdt_bark", &wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) wdt->wdd.info = &qcom_wdt_pt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) wdt->wdd.pretimeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) wdt->wdd.info = &qcom_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) wdt->wdd.ops = &qcom_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wdt->wdd.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) wdt->wdd.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) wdt->layout = data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (readl(wdt_addr(wdt, WDT_STS)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wdt->wdd.bootstatus = WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * If 'timeout-sec' unspecified in devicetree, assume a 30 second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * default, unless the max timeout is less than 30 seconds, then use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * the max instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) watchdog_init_timeout(&wdt->wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = devm_watchdog_register_device(dev, &wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int __maybe_unused qcom_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct qcom_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) qcom_wdt_stop(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int __maybe_unused qcom_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct qcom_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (watchdog_active(&wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) qcom_wdt_start(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct of_device_id qcom_wdt_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct platform_driver qcom_watchdog_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .probe = qcom_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .of_match_table = qcom_wdt_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .pm = &qcom_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) module_platform_driver(qcom_watchdog_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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