^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PON_INT_RT_STS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PMIC_WD_BARK_STS_BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PON_PMIC_WD_RESET_S1_TIMER 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PON_PMIC_WD_RESET_S2_TIMER 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PON_PMIC_WD_RESET_S2_CTL 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RESET_TYPE_WARM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_TYPE_SHUTDOWN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_TYPE_HARD 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PON_PMIC_WD_RESET_S2_CTL2 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S2_RESET_EN_BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PON_PMIC_WD_RESET_PET 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WATCHDOG_PET_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PM8916_WDT_DEFAULT_TIMEOUT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PM8916_WDT_MIN_TIMEOUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PM8916_WDT_MAX_TIMEOUT 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct pm8916_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct watchdog_device wdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int pm8916_wdt_start(struct watchdog_device *wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return regmap_update_bits(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) S2_RESET_EN_BIT, S2_RESET_EN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int pm8916_wdt_stop(struct watchdog_device *wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return regmap_update_bits(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) S2_RESET_EN_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int pm8916_wdt_ping(struct watchdog_device *wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return regmap_update_bits(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) wdt->baseaddr + PON_PMIC_WD_RESET_PET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) WATCHDOG_PET_BIT, WATCHDOG_PET_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int pm8916_wdt_configure_timers(struct watchdog_device *wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) err = regmap_write(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) wdt->baseaddr + PON_PMIC_WD_RESET_S1_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) wdev->timeout - wdev->pretimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return regmap_write(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) wdt->baseaddr + PON_PMIC_WD_RESET_S2_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) wdev->pretimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int pm8916_wdt_set_timeout(struct watchdog_device *wdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) wdev->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return pm8916_wdt_configure_timers(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int pm8916_wdt_set_pretimeout(struct watchdog_device *wdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int pretimeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) wdev->pretimeout = pretimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return pm8916_wdt_configure_timers(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static irqreturn_t pm8916_wdt_isr(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pm8916_wdt *wdt = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int err, sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err = regmap_read(wdt->regmap, wdt->baseaddr + PON_INT_RT_STS, &sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (sts & PMIC_WD_BARK_STS_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) watchdog_notify_pretimeout(&wdt->wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct watchdog_info pm8916_wdt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .identity = "QCOM PM8916 PON WDT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct watchdog_info pm8916_wdt_pt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) WDIOF_PRETIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .identity = "QCOM PM8916 PON WDT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct watchdog_ops pm8916_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .start = pm8916_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .stop = pm8916_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .ping = pm8916_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .set_timeout = pm8916_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .set_pretimeout = pm8916_wdt_set_pretimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int pm8916_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pm8916_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * The pm8916-pon-wdt is a child of the pon device, which is a child
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * of the pm8916 mfd device. We want access to the pm8916 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Retrieve regmap from pm8916 (parent->parent) and base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * from pm8916-pon (pon).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) wdt->regmap = dev_get_regmap(parent->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!wdt->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(dev, "failed to locate regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) err = device_property_read_u32(parent, "reg", &wdt->baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dev, "failed to get pm8916-pon address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) err = devm_request_irq(dev, irq, pm8916_wdt_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "pm8916_wdt", wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) wdt->wdev.info = &pm8916_wdt_pt_ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) wdt->wdev.info = &pm8916_wdt_ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Configure watchdog to hard-reset mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) err = regmap_write(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) RESET_TYPE_HARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(dev, "failed configure watchdog\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) wdt->wdev.ops = &pm8916_wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) wdt->wdev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) wdt->wdev.min_timeout = PM8916_WDT_MIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) wdt->wdev.max_timeout = PM8916_WDT_MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) wdt->wdev.timeout = PM8916_WDT_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) wdt->wdev.pretimeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) watchdog_set_drvdata(&wdt->wdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) watchdog_init_timeout(&wdt->wdev, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pm8916_wdt_configure_timers(&wdt->wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return devm_watchdog_register_device(dev, &wdt->wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int __maybe_unused pm8916_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pm8916_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (watchdog_active(&wdt->wdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return pm8916_wdt_stop(&wdt->wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int __maybe_unused pm8916_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct pm8916_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (watchdog_active(&wdt->wdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return pm8916_wdt_start(&wdt->wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static SIMPLE_DEV_PM_OPS(pm8916_wdt_pm_ops, pm8916_wdt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pm8916_wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct of_device_id pm8916_wdt_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .compatible = "qcom,pm8916-wdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_DEVICE_TABLE(of, pm8916_wdt_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct platform_driver pm8916_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .probe = pm8916_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .name = "pm8916-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .of_match_table = of_match_ptr(pm8916_wdt_id_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .pm = &pm8916_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) module_platform_driver(pm8916_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_DESCRIPTION("Qualcomm pm8916 watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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