^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PIC32 deadman timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Purna Chandra Mandal <purna.mandal@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2016, Microchip Technology Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach-pic32/pic32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Deadman Timer Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMTCON_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMTPRECLR_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMTCLR_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMTSTAT_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DMTCNT_REG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DMTPSCNT_REG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMTPSINTV_REG 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Deadman Timer Regs fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DMT_ON BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMT_STEP1_KEY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMT_STEP2_KEY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMTSTAT_WINOPN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMTSTAT_EVENT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMTSTAT_BAD2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DMTSTAT_BAD1 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Reset Control Register fields for watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RESETCON_DMT_TIMEOUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct pic32_dmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void dmt_enable(struct pic32_dmt *dmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline void dmt_disable(struct pic32_dmt *dmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Cannot touch registers in the CPU cycle following clearing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * ON bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline int dmt_bad_status(struct pic32_dmt *dmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val = readl(dmt->regs + DMTSTAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val &= (DMTSTAT_BAD1 | DMTSTAT_BAD2 | DMTSTAT_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline int dmt_keepalive(struct pic32_dmt *dmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 timeout = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* set pre-clear key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* wait for DMT window to open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (v == DMTSTAT_WINOPN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* apply key2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* check whether keys are latched correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return dmt_bad_status(dmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rate = clk_get_rate(dmt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return readl(dmt->regs + DMTPSCNT_REG) / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *rst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rst_base = ioremap(PIC32_BASE_RESET, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!rst_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) v = readl(rst_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iounmap(rst_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return v & RESETCON_DMT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int pic32_dmt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dmt_enable(dmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return dmt_keepalive(dmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int pic32_dmt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dmt_disable(dmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int pic32_dmt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return dmt_keepalive(dmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct watchdog_ops pic32_dmt_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .start = pic32_dmt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .stop = pic32_dmt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ping = pic32_dmt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct watchdog_info pic32_dmt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .options = WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .identity = "PIC32 Deadman Timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct watchdog_device pic32_dmt_wdd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .info = &pic32_dmt_ident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .ops = &pic32_dmt_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void pic32_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int pic32_dmt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct pic32_dmt *dmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct watchdog_device *wdd = &pic32_dmt_wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dmt = devm_kzalloc(dev, sizeof(*dmt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!dmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dmt->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (IS_ERR(dmt->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return PTR_ERR(dmt->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dmt->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (IS_ERR(dmt->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(dev, "clk not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return PTR_ERR(dmt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = clk_prepare_enable(dmt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dmt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) wdd->timeout = pic32_dmt_get_timeout_secs(dmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!wdd->timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(dev, "failed to read watchdog register timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_info(dev, "timeout %d\n", wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) watchdog_set_drvdata(wdd, dmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = devm_watchdog_register_device(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) platform_set_drvdata(pdev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct of_device_id pic32_dmt_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .compatible = "microchip,pic32mzda-dmt",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_DEVICE_TABLE(of, pic32_dmt_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct platform_driver pic32_dmt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .probe = pic32_dmt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "pic32-dmt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .of_match_table = of_match_ptr(pic32_dmt_of_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) module_platform_driver(pic32_dmt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_DESCRIPTION("Microchip PIC32 DMT Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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