^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/watchdog/orion_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Watchdog driver for Orion/Kirkwood processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Sylver Bruneau <sylver.bruneau@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ORION_RSTOUT_MASK_OFFSET 0x20108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Internal registers can be configured at any 1 MiB aligned address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INTERNAL_REGS_MASK ~(SZ_1M - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Watchdog timer block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIMER_CTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TIMER1_FIXED_ENABLE_BIT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TIMER1_ENABLE_BIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TIMER_A370_STATUS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WDT_A370_EXPIRED BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TIMER1_STATUS_BIT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TIMER1_VAL_OFF 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WDT_MAX_CYCLE_COUNT 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WDT_A370_RATIO_MASK(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WDT_A370_RATIO_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WDT_A370_RATIO (1 << WDT_A370_RATIO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int heartbeat; /* module parameter (seconds) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct orion_watchdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct orion_watchdog_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int wdt_counter_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int wdt_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int rstout_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int rstout_mask_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int (*clock_init)(struct platform_device *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct orion_watchdog *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int (*enabled)(struct orion_watchdog *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int (*start)(struct watchdog_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int (*stop)(struct watchdog_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct orion_watchdog {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct watchdog_device wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *rstout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *rstout_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct orion_watchdog_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int orion_wdt_clock_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct orion_watchdog *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (IS_ERR(dev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_put(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev->clk_rate = clk_get_rate(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int armada370_wdt_clock_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct orion_watchdog *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (IS_ERR(dev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk_put(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Setup watchdog input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) atomic_io_modify(dev->reg + TIMER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int armada375_wdt_clock_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct orion_watchdog *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!IS_ERR(dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clk_put(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) atomic_io_modify(dev->reg + TIMER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) WDT_AXP_FIXED_ENABLE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) WDT_AXP_FIXED_ENABLE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev->clk_rate = clk_get_rate(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Mandatory fallback for proper devicetree backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (IS_ERR(dev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk_put(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) atomic_io_modify(dev->reg + TIMER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int armadaxp_wdt_clock_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct orion_watchdog *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (IS_ERR(dev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk_put(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Fix the wdt and timer1 clock freqency to 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val = WDT_AXP_FIXED_ENABLE_BIT | TIMER1_FIXED_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) atomic_io_modify(dev->reg + TIMER_CTRL, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev->clk_rate = clk_get_rate(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int orion_wdt_ping(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Reload watchdog duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(dev->clk_rate * wdt_dev->timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev->reg + dev->data->wdt_counter_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (dev->wdt.info->options & WDIOF_PRETIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev->reg + TIMER1_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int armada375_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Set watchdog duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(dev->clk_rate * wdt_dev->timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev->reg + dev->data->wdt_counter_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (dev->wdt.info->options & WDIOF_PRETIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev->reg + TIMER1_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Clear the watchdog expiration bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Enable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = dev->data->wdt_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (dev->wdt.info->options & WDIOF_PRETIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg |= TIMER1_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) atomic_io_modify(dev->reg + TIMER_CTRL, reg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Enable reset on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg = readl(dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg |= dev->data->rstout_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(reg, dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int armada370_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Set watchdog duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(dev->clk_rate * wdt_dev->timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev->reg + dev->data->wdt_counter_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Clear the watchdog expiration bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Enable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev->data->wdt_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Enable reset on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg = readl(dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reg |= dev->data->rstout_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(reg, dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int orion_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Set watchdog duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel(dev->clk_rate * wdt_dev->timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev->reg + dev->data->wdt_counter_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Enable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev->data->wdt_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Enable reset on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev->data->rstout_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int orion_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* There are some per-SoC quirks to handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return dev->data->start(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int orion_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Disable reset on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Disable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int armada375_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Disable reset on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev->data->rstout_mask_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg = readl(dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) reg &= ~dev->data->rstout_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) writel(reg, dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Disable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mask = dev->data->wdt_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (wdt_dev->info->options & WDIOF_PRETIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mask |= TIMER1_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) atomic_io_modify(dev->reg + TIMER_CTRL, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int armada370_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Disable reset on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) reg = readl(dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) reg &= ~dev->data->rstout_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) writel(reg, dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Disable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int orion_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return dev->data->stop(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int orion_enabled(struct orion_watchdog *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) bool enabled, running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return enabled && running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int armada375_enabled(struct orion_watchdog *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bool masked, enabled, running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) masked = readl(dev->rstout_mask) & dev->data->rstout_mask_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return !masked && enabled && running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int orion_wdt_enabled(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return dev->data->enabled(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct watchdog_info orion_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .identity = "Orion Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct watchdog_ops orion_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .start = orion_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .stop = orion_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .ping = orion_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .get_timeleft = orion_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static irqreturn_t orion_wdt_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) panic("Watchdog Timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static irqreturn_t orion_wdt_pre_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct orion_watchdog *dev = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) atomic_io_modify(dev->reg + TIMER_A370_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) TIMER1_STATUS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) watchdog_notify_pretimeout(&dev->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * The original devicetree binding for this driver specified only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * one memory resource, so in order to keep DT backwards compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * we try to fallback to a hardcoded register address, if the resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * is missing from the devicetree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) phys_addr_t internal_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) phys_addr_t rstout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) WARN(1, FW_BUG "falling back to hardcoded RSTOUT reg %pa\n", &rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return devm_ioremap(&pdev->dev, rstout, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct orion_watchdog_data orion_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .rstout_enable_bit = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .wdt_enable_bit = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .wdt_counter_offset = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .clock_init = orion_wdt_clock_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .enabled = orion_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .start = orion_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .stop = orion_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct orion_watchdog_data armada370_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .rstout_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .wdt_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .wdt_counter_offset = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .clock_init = armada370_wdt_clock_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .enabled = orion_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .start = armada370_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .stop = armada370_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct orion_watchdog_data armadaxp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .rstout_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .wdt_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .wdt_counter_offset = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .clock_init = armadaxp_wdt_clock_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .enabled = orion_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .start = armada370_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .stop = armada370_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct orion_watchdog_data armada375_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .rstout_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .rstout_mask_bit = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .wdt_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .wdt_counter_offset = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .clock_init = armada375_wdt_clock_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .enabled = armada375_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .start = armada375_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .stop = armada375_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct orion_watchdog_data armada380_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .rstout_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .rstout_mask_bit = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .wdt_enable_bit = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .wdt_counter_offset = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .clock_init = armadaxp_wdt_clock_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .enabled = armada375_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .start = armada375_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .stop = armada375_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct of_device_id orion_wdt_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .compatible = "marvell,orion-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .data = &orion_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .compatible = "marvell,armada-370-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .data = &armada370_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .compatible = "marvell,armada-xp-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .data = &armadaxp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .compatible = "marvell,armada-375-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .data = &armada375_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .compatible = "marvell,armada-380-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .data = &armada380_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int orion_wdt_get_regs(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct orion_watchdog *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev->reg = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!dev->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Each supported compatible has some RSTOUT register quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (of_device_is_compatible(node, "marvell,orion-wdt")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) INTERNAL_REGS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!dev->rstout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else if (of_device_is_compatible(node, "marvell,armada-370-wdt") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) of_device_is_compatible(node, "marvell,armada-xp-wdt")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Dedicated RSTOUT register, can be requested. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev->rstout = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (IS_ERR(dev->rstout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return PTR_ERR(dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else if (of_device_is_compatible(node, "marvell,armada-375-wdt") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) of_device_is_compatible(node, "marvell,armada-380-wdt")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Dedicated RSTOUT register, can be requested. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev->rstout = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(dev->rstout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return PTR_ERR(dev->rstout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev->rstout_mask = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!dev->rstout_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int orion_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct orion_watchdog *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int wdt_max_duration; /* (seconds) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) match = of_match_device(orion_wdt_of_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Default legacy match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) match = &orion_wdt_of_match_table[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev->wdt.info = &orion_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev->wdt.ops = &orion_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev->wdt.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev->data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = orion_wdt_get_regs(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = dev->data->clock_init(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(&pdev->dev, "cannot initialize clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev->wdt.timeout = wdt_max_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev->wdt.max_timeout = wdt_max_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev->wdt.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) platform_set_drvdata(pdev, &dev->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) watchdog_set_drvdata(&dev->wdt, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Let's make sure the watchdog is fully stopped, unless it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * explicitly enabled. This may be the case if the module was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * removed and re-inserted, or if the bootloader explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * set a running watchdog before booting the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!orion_wdt_enabled(&dev->wdt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) orion_wdt_stop(&dev->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) set_bit(WDOG_HW_RUNNING, &dev->wdt.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Request the IRQ only after the watchdog is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) irq = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * Not all supported platforms specify an interrupt for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * watchdog, so let's make it optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) pdev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_err(&pdev->dev, "failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Optional 2nd interrupt for pretimeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) irq = platform_get_irq_optional(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) orion_wdt_info.options |= WDIOF_PRETIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = devm_request_irq(&pdev->dev, irq, orion_wdt_pre_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0, pdev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(&pdev->dev, "failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) watchdog_set_nowayout(&dev->wdt, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = watchdog_register_device(&dev->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pr_info("Initial timeout %d sec%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev->wdt.timeout, nowayout ? ", nowayout" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) clk_put(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int orion_wdt_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) watchdog_unregister_device(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) clk_put(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void orion_wdt_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) orion_wdt_stop(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct platform_driver orion_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .probe = orion_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .remove = orion_wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .shutdown = orion_wdt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .name = "orion_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .of_match_table = orion_wdt_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) module_platform_driver(orion_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_DESCRIPTION("Orion Processor Watchdog");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MODULE_ALIAS("platform:orion_wdt");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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