Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * omap_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	 <gdavis@mvista.com> or <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * 2003 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * 20030527: George G. Davis <gdavis@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *	Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Copyright (c) 2004 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *	1. Modified to support OMAP1610 32-KHz watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *	2. Ported to 2.6 kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Copyright (c) 2005 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *	Use the driver model and standard identifiers; handle bigger timeouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/platform_data/omap-wd-timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include "omap_wdt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static unsigned timer_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) module_param(timer_margin, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define to_omap_wdt_dev(_wdog)	container_of(_wdog, struct omap_wdt_dev, wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static bool early_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) module_param(early_enable, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) MODULE_PARM_DESC(early_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	"Watchdog is started on module insertion (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct omap_wdt_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct watchdog_device wdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	void __iomem    *base;          /* physical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct device   *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	bool		omap_wdt_users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int		wdt_trgr_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct mutex	lock;		/* to avoid races with PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void omap_wdt_reload(struct omap_wdt_dev *wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	void __iomem    *base = wdev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* wait for posted write to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* wait for posted write to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* reloaded WCRR from WLDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void omap_wdt_enable(struct omap_wdt_dev *wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	void __iomem *base = wdev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* Sequence to enable the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void omap_wdt_disable(struct omap_wdt_dev *wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	void __iomem *base = wdev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* sequence required to disable watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				   unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 pre_margin = GET_WLDR_VAL(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	void __iomem *base = wdev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* just count up at 32 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int omap_wdt_start(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	void __iomem *base = wdev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mutex_lock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	wdev->omap_wdt_users = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pm_runtime_get_sync(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * Make sure the watchdog is disabled. This is unfortunately required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 * because writing to various registers with the watchdog running has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	omap_wdt_disable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* initialize prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	omap_wdt_set_timer(wdev, wdog->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	omap_wdt_enable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	mutex_unlock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int omap_wdt_stop(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	mutex_lock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	omap_wdt_disable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pm_runtime_put_sync(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	wdev->omap_wdt_users = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	mutex_unlock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int omap_wdt_ping(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mutex_lock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	omap_wdt_reload(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	mutex_unlock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int omap_wdt_set_timeout(struct watchdog_device *wdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	mutex_lock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	omap_wdt_disable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	omap_wdt_set_timer(wdev, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	omap_wdt_enable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	omap_wdt_reload(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	wdog->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mutex_unlock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	void __iomem *base = wdev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return GET_WCCR_SECS(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct watchdog_info omap_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.identity = "OMAP Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct watchdog_ops omap_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.start		= omap_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.stop		= omap_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.ping		= omap_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.set_timeout	= omap_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.get_timeleft	= omap_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int omap_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct omap_wdt_dev *wdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (!wdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	wdev->omap_wdt_users	= false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	wdev->dev		= &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	wdev->wdt_trgr_pattern	= 0x1234;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mutex_init(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* reserve static register mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	wdev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (IS_ERR(wdev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return PTR_ERR(wdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	wdev->wdog.info = &omap_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	wdev->wdog.ops = &omap_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	wdev->wdog.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	watchdog_set_nowayout(&wdev->wdog, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	platform_set_drvdata(pdev, wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	pm_runtime_enable(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	pm_runtime_get_sync(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (pdata && pdata->read_reset_sources) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		u32 rs = pdata->read_reset_sources();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			wdev->wdog.bootstatus = WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (early_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		omap_wdt_start(&wdev->wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		set_bit(WDOG_HW_RUNNING, &wdev->wdog.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		omap_wdt_disable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ret = watchdog_register_device(&wdev->wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		pm_runtime_put(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		pm_runtime_disable(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		wdev->wdog.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (early_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		omap_wdt_start(&wdev->wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	pm_runtime_put(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void omap_wdt_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	mutex_lock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (wdev->omap_wdt_users) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		omap_wdt_disable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		pm_runtime_put_sync(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	mutex_unlock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int omap_wdt_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	pm_runtime_disable(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	watchdog_unregister_device(&wdev->wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifdef	CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* REVISIT ... not clear this is the best way to handle system suspend; and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  * it's very inappropriate for selective device suspend (e.g. suspending this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * through sysfs rather than by stopping the watchdog daemon).  Also, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  * may not play well enough with NOWAYOUT...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	mutex_lock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (wdev->omap_wdt_users) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		omap_wdt_disable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		pm_runtime_put_sync(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	mutex_unlock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int omap_wdt_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	mutex_lock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (wdev->omap_wdt_users) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		pm_runtime_get_sync(wdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		omap_wdt_enable(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		omap_wdt_reload(wdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	mutex_unlock(&wdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define	omap_wdt_suspend	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define	omap_wdt_resume		NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct of_device_id omap_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	{ .compatible = "ti,omap3-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct platform_driver omap_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.probe		= omap_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.remove		= omap_wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.shutdown	= omap_wdt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.suspend	= omap_wdt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.resume		= omap_wdt_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.name	= "omap_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.of_match_table = omap_wdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) module_platform_driver(omap_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_AUTHOR("George G. Davis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_ALIAS("platform:omap_wdt");