Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (C) Copyright 2013 - 2014 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Register offsets for the Wdt device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* Control/Status Register Masks  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define XWT_CSR0_WRS_MASK   0x00000008 /* Reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define XWT_CSR0_WDS_MASK   0x00000004 /* Timer state  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Control/Status Register 0/1 bits  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* SelfTest constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define XWT_TIMER_FAILED            0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WATCHDOG_NAME     "Xilinx Watchdog"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct xwdt_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 wdt_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	spinlock_t spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct watchdog_device xilinx_wdt_wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int xilinx_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 control_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	ret = clk_enable(xdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		dev_err(wdd->parent, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	spin_lock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/* Clean previous status and enable the watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		  xdev->base + XWT_TWCSR0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	spin_unlock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int xilinx_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 control_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	spin_lock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		  xdev->base + XWT_TWCSR0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	spin_unlock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	clk_disable(xdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	pr_info("Stopped!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u32 control_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	spin_lock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	spin_unlock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct watchdog_info xilinx_wdt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.options =  WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		    WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.firmware_version =	1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.identity =	WATCHDOG_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct watchdog_ops xilinx_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.start = xilinx_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.stop = xilinx_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.ping = xilinx_wdt_keepalive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static u32 xwdt_selftest(struct xwdt_device *xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 timer_value1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 timer_value2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	spin_lock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	for (i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			(timer_value2 == timer_value1)); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	spin_unlock(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (timer_value2 != timer_value1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return ~XWT_TIMER_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return XWT_TIMER_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void xwdt_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int xwdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 pfreq = 0, enable_once = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct xwdt_device *xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct watchdog_device *xilinx_wdt_wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (!xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	xilinx_wdt_wdd->info = &xilinx_wdt_ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	xilinx_wdt_wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	xdev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (IS_ERR(xdev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return PTR_ERR(xdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				  &xdev->wdt_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				  &enable_once);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			 "Parameter \"xlnx,wdt-enable-once\" not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	xdev->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (IS_ERR(xdev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		if (PTR_ERR(xdev->clk) != -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			return PTR_ERR(xdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		 * Clock framework support is optional, continue on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		 * anyways if we don't find a matching clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		xdev->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		rc = of_property_read_u32(dev->of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					  &pfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				 "The watchdog clock freq cannot be obtained\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		pfreq = clk_get_rate(xdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * Twice of the 2^wdt_interval / freq  because the first wdt overflow is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * ignored (interrupt), reset is only generated at second wdt overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (pfreq && xdev->wdt_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 					  pfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	spin_lock_init(&xdev->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	rc = clk_prepare_enable(xdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		dev_err(dev, "unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	rc = devm_add_action_or_reset(dev, xwdt_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				      xdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	rc = xwdt_selftest(xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (rc == XWT_TIMER_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_err(dev, "SelfTest routine error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	clk_disable(xdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	dev_info(dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		 xdev->base, xilinx_wdt_wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	platform_set_drvdata(pdev, xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * xwdt_suspend - Suspend the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * @dev: handle to the device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * Return: 0 always.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int __maybe_unused xwdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct xwdt_device *xdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (watchdog_active(&xdev->xilinx_wdt_wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * xwdt_resume - Resume the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * @dev: handle to the device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * Return: 0 on success, errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int __maybe_unused xwdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct xwdt_device *xdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (watchdog_active(&xdev->xilinx_wdt_wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Match table for of_platform binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct of_device_id xwdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_DEVICE_TABLE(of, xwdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct platform_driver xwdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.probe       = xwdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.name  = WATCHDOG_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.of_match_table = xwdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.pm = &xwdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) module_platform_driver(xwdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_DESCRIPTION("Xilinx Watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_LICENSE("GPL");