Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	nv_tco:	TCO timer driver for nVidia chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	(c) Copyright 2005 Google Inc., All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	Supported Chipsets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *		- MCP51/MCP55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	(c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *	Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *				https://www.kernelconcepts.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *	Neither kernel concepts nor Nils Faerber admit liability nor provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *	warranty for any of this software. This material is provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *	"AS-IS" and at no charge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *	(c) Copyright 2000	kernel concepts <nils@kernelconcepts.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *				developed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *                              Jentro AG, Haar/Munich (Germany)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *	TCO timer driver for NV chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *	based on softdog.c by Alan Cox <alan@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * Some address definitions for the TCO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TCO_RLD(base)	((base) + 0x00)	/* TCO Timer Reload and Current Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TCO_TMR(base)	((base) + 0x01)	/* TCO Timer Initial Value	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TCO_STS(base)	((base) + 0x04)	/* TCO Status Register		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * TCO Boot Status bit: set on TCO reset, reset by software or standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * power-good (survives reboots), unfortunately this bit is never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #  define TCO_STS_BOOT_STS	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * first and 2nd timeout status bits, these also survive a warm boot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * and they work, so we use them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #  define TCO_STS_TCO_INT_STS	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #  define TCO_STS_TCO2TO_STS	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #  define TCO_STS_RESET		(TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 				 TCO_STS_TCO_INT_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TCO_CNT(base)	((base) + 0x08)	/* TCO Control Register	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #  define TCO_CNT_TCOHALT	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCP51_SMBUS_SETUP_B 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #  define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  * The SMI_EN register is at the base io address + 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  * while TCOBASE is + 0x40.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCP51_SMI_EN(base)	((base) - 0x40 + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #  define MCP51_SMI_EN_TCO	((1 << 4) | (1 << 5))