Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (c) 2018 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2018 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define NPCM_WTCR	0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define NPCM_WTCLK	(BIT(10) | BIT(11))	/* Clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define NPCM_WTE	BIT(7)			/* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define NPCM_WTIE	BIT(6)			/* Enable irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define NPCM_WTIS	(BIT(4) | BIT(5))	/* Interval selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define NPCM_WTIF	BIT(3)			/* Interrupt flag*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define NPCM_WTRF	BIT(2)			/* Reset flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define NPCM_WTRE	BIT(1)			/* Reset enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define NPCM_WTR	BIT(0)			/* Reset counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Watchdog timeouts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * 170     msec:    WTCLK=01 WTIS=00     VAL= 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * 670     msec:    WTCLK=01 WTIS=01     VAL= 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * 1360    msec:    WTCLK=10 WTIS=00     VAL= 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * 2700    msec:    WTCLK=01 WTIS=10     VAL= 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * 5360    msec:    WTCLK=10 WTIS=01     VAL= 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * 10700   msec:    WTCLK=01 WTIS=11     VAL= 0x430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * 21600   msec:    WTCLK=10 WTIS=10     VAL= 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * 43000   msec:    WTCLK=11 WTIS=00     VAL= 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * 85600   msec:    WTCLK=10 WTIS=11     VAL= 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * 172000  msec:    WTCLK=11 WTIS=01     VAL= 0xC10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * 687000  msec:    WTCLK=11 WTIS=10     VAL= 0xC20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * 2750000 msec:    WTCLK=11 WTIS=11     VAL= 0xC30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct npcm_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct watchdog_device  wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	void __iomem		*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return container_of(wdd, struct npcm_wdt, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int npcm_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct npcm_wdt *wdt = to_npcm_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	val = readl(wdt->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	writel(val | NPCM_WTR, wdt->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int npcm_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct npcm_wdt *wdt = to_npcm_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (wdd->timeout < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		val = 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	else if (wdd->timeout < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		val = 0x420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	else if (wdd->timeout < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		val = 0x810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	else if (wdd->timeout < 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		val = 0x430;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	else if (wdd->timeout < 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		val = 0x820;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	else if (wdd->timeout < 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		val = 0xC00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	else if (wdd->timeout < 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		val = 0x830;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	else if (wdd->timeout < 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		val = 0xC10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	else if (wdd->timeout < 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		val = 0xC20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		val = 0xC30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	writel(val, wdt->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int npcm_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct npcm_wdt *wdt = to_npcm_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	writel(0, wdt->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int npcm_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (timeout < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		wdd->timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	else if (timeout < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		wdd->timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	else if (timeout < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		wdd->timeout = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	else if (timeout < 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		wdd->timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	else if (timeout < 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		wdd->timeout = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	else if (timeout < 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		wdd->timeout = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	else if (timeout < 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		wdd->timeout = 86;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	else if (timeout < 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		wdd->timeout = 172;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	else if (timeout < 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		wdd->timeout = 687;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		wdd->timeout = 2750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (watchdog_active(wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		npcm_wdt_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static irqreturn_t npcm_wdt_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct npcm_wdt *wdt = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	watchdog_notify_pretimeout(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int npcm_wdt_restart(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			    unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct npcm_wdt *wdt = to_npcm_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static bool npcm_is_running(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct npcm_wdt *wdt = to_npcm_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return readl(wdt->reg) & NPCM_WTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct watchdog_info npcm_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.identity	= KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.options	= WDIOF_SETTIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			| WDIOF_KEEPALIVEPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			| WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct watchdog_ops npcm_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.start = npcm_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.stop = npcm_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.ping = npcm_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.set_timeout = npcm_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.restart = npcm_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int npcm_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct npcm_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	wdt->reg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (IS_ERR(wdt->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return PTR_ERR(wdt->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	wdt->wdd.info = &npcm_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	wdt->wdd.ops = &npcm_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	wdt->wdd.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	wdt->wdd.max_timeout = 2750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	wdt->wdd.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	wdt->wdd.timeout = 86;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	watchdog_init_timeout(&wdt->wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* Ensure timeout is able to be represented by the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (npcm_is_running(&wdt->wdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		/* Restart with the default or device-tree specified timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		npcm_wdt_start(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = devm_request_irq(dev, irq, npcm_wdt_interrupt, 0, "watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			       wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = devm_watchdog_register_device(dev, &wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	dev_info(dev, "NPCM watchdog driver enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id npcm_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{.compatible = "nuvoton,npcm750-wdt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(of, npcm_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct platform_driver npcm_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.probe		= npcm_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.name	= "npcm-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.of_match_table = of_match_ptr(npcm_wdt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) module_platform_driver(npcm_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_AUTHOR("Joel Stanley");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_DESCRIPTION("Watchdog driver for NPCM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_LICENSE("GPL v2");