Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Mediatek Watchdog Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Matthias Brugger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Matthias Brugger <matthias.bgg@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Based on sunxi_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <dt-bindings/reset-controller/mt2712-resets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <dt-bindings/reset-controller/mt8183-resets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define WDT_MAX_TIMEOUT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define WDT_MIN_TIMEOUT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define WDT_LENGTH_TIMEOUT(n)	((n) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define WDT_LENGTH		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define WDT_LENGTH_KEY		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WDT_RST			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WDT_RST_RELOAD		0x1971
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WDT_MODE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WDT_MODE_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WDT_MODE_EXT_POL_LOW	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WDT_MODE_EXT_POL_HIGH	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WDT_MODE_EXRST_EN	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WDT_MODE_IRQ_EN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WDT_MODE_AUTO_START	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WDT_MODE_DUAL_EN	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WDT_MODE_KEY		0x22000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WDT_SWRST		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WDT_SWRST_KEY		0x1209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WDT_SWSYSRST		0x18U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WDT_SWSYS_RST_KEY	0x88000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DRV_NAME		"mtk-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DRV_VERSION		"1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) struct mtk_wdt_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct watchdog_device wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void __iomem *wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	spinlock_t lock; /* protects WDT_SWSYSRST reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct mtk_wdt_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int toprgu_sw_rst_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static const struct mtk_wdt_data mt2712_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static const struct mtk_wdt_data mt8183_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int toprgu_reset_update(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			       unsigned long id, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct mtk_wdt_dev *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		 container_of(rcdev, struct mtk_wdt_dev, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	tmp = readl(data->wdt_base + WDT_SWSYSRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		tmp |= BIT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		tmp &= ~BIT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	tmp |= WDT_SWSYS_RST_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	writel(tmp, data->wdt_base + WDT_SWSYSRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			       unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return toprgu_reset_update(rcdev, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				 unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return toprgu_reset_update(rcdev, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int toprgu_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret = toprgu_reset_assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return toprgu_reset_deassert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct reset_control_ops toprgu_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.assert = toprgu_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.deassert = toprgu_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.reset = toprgu_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int toprgu_register_reset_controller(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 					    int rst_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	spin_lock_init(&mtk_wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	mtk_wdt->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mtk_wdt->rcdev.nr_resets = rst_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mtk_wdt->rcdev.ops = &toprgu_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mtk_wdt->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			"couldn't register wdt reset controller: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			   unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	void __iomem *wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	wdt_base = mtk_wdt->wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	void __iomem *wdt_base = mtk_wdt->wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	void __iomem *wdt_base = mtk_wdt->wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	wdt_dev->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * One bit is the value of 512 ticks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 * The clock has 32 KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	reg = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	iowrite32(reg, wdt_base + WDT_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	mtk_wdt_ping(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	void __iomem *wdt_base = mtk_wdt->wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	reg = readl(wdt_base + WDT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	reg &= ~WDT_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	reg |= WDT_MODE_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	iowrite32(reg, wdt_base + WDT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mtk_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	void __iomem *wdt_base = mtk_wdt->wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	reg = ioread32(wdt_base + WDT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	reg |= (WDT_MODE_EN | WDT_MODE_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	iowrite32(reg, wdt_base + WDT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct watchdog_info mtk_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.identity	= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.options	= WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			  WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			  WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct watchdog_ops mtk_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.start		= mtk_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.stop		= mtk_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.ping		= mtk_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.set_timeout	= mtk_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.restart	= mtk_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int mtk_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct mtk_wdt_dev *mtk_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	const struct mtk_wdt_data *wdt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!mtk_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	platform_set_drvdata(pdev, mtk_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (IS_ERR(mtk_wdt->wdt_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return PTR_ERR(mtk_wdt->wdt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	mtk_wdt->wdt_dev.info = &mtk_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mtk_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	mtk_wdt->wdt_dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	mtk_wdt_stop(&mtk_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		 mtk_wdt->wdt_dev.timeout, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	wdt_data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (wdt_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		err = toprgu_register_reset_controller(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 						       wdt_data->toprgu_sw_rst_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int mtk_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (watchdog_active(&mtk_wdt->wdt_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		mtk_wdt_stop(&mtk_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int mtk_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (watchdog_active(&mtk_wdt->wdt_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		mtk_wdt_start(&mtk_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		mtk_wdt_ping(&mtk_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct of_device_id mtk_wdt_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	{ .compatible = "mediatek,mt6589-wdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct dev_pm_ops mtk_wdt_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 				mtk_wdt_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct platform_driver mtk_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.probe		= mtk_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.pm		= &mtk_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.of_match_table	= mtk_wdt_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) module_platform_driver(mtk_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) module_param(timeout, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_VERSION(DRV_VERSION);