Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Ralink MT7621/MT7628 built-in hardware watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This driver was based on: drivers/watchdog/rt2880_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SYSC_RSTSTAT			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define WDT_RST_CAUSE			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RALINK_WDT_TIMEOUT		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TIMER_REG_TMRSTAT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TIMER_REG_TMR1LOAD		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TIMER_REG_TMR1CTL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TMR1CTL_ENABLE			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TMR1CTL_RESTART			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TMR1CTL_PRESCALE_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void __iomem *mt7621_wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static struct reset_control *mt7621_wdt_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		 "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static inline void rt_wdt_w32(unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	iowrite32(val, mt7621_wdt_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static inline u32 rt_wdt_r32(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return ioread32(mt7621_wdt_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int mt7621_wdt_ping(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	w->timeout = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	mt7621_wdt_ping(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int mt7621_wdt_start(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* set the prescaler to 1ms == 1000us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mt7621_wdt_set_timeout(w, w->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	t |= TMR1CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int mt7621_wdt_stop(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	mt7621_wdt_ping(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	t &= ~TMR1CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int mt7621_wdt_bootcause(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int mt7621_wdt_is_running(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct watchdog_info mt7621_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.identity = "Mediatek Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct watchdog_ops mt7621_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.start = mt7621_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.stop = mt7621_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.ping = mt7621_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.set_timeout = mt7621_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct watchdog_device mt7621_wdt_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.info = &mt7621_wdt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.ops = &mt7621_wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.min_timeout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.max_timeout = 0xfffful / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int mt7621_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (IS_ERR(mt7621_wdt_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return PTR_ERR(mt7621_wdt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (!IS_ERR(mt7621_wdt_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		reset_control_deassert(mt7621_wdt_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			      dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		 * Make sure to apply timeout from watchdog core, taking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		 * the prescaler of this driver here into account (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		 * boot loader might be using a different prescaler).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		 * To avoid spurious resets because of different scaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 * we first disable the watchdog, set the new prescaler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 * and timeout, and then re-enable the watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		mt7621_wdt_stop(&mt7621_wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		mt7621_wdt_start(&mt7621_wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return devm_watchdog_register_device(dev, &mt7621_wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void mt7621_wdt_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	mt7621_wdt_stop(&mt7621_wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct of_device_id mt7621_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ .compatible = "mediatek,mt7621-wdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct platform_driver mt7621_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.probe		= mt7621_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.shutdown	= mt7621_wdt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.name		= KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.of_match_table	= mt7621_wdt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) module_platform_driver(mt7621_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_AUTHOR("John Crispin <john@phrozen.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MODULE_LICENSE("GPL v2");