Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors: Dave Updegraff <dave@cray.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	    Kumar Gala <galak@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *		Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *				..and from sc520_wdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (c) 2008  MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *                     Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Note: it appears that you can only actually ENABLE or DISABLE the thing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * once after POR. Once enabled, you cannot disable, and vice versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define WATCHDOG_TIMEOUT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct mpc8xxx_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	__be32 res0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	__be32 swcrr; /* System watchdog control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SWCRR_SWF  0x00000008 /* Software Watchdog Freeze (mpc8xx). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	__be32 swcnr; /* System watchdog count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u8 res1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	__be16 swsrr; /* System watchdog service register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u8 res2[0xF0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct mpc8xxx_wdt_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	bool hw_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 rsr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct mpc8xxx_wdt_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct mpc8xxx_wdt __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u16 swtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static u16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) module_param(timeout, ushort, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) MODULE_PARM_DESC(timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	"Watchdog timeout in seconds. (1<timeout<65535, default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static bool reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) module_param(reset, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) MODULE_PARM_DESC(reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	"Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* Ping the WDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	spin_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	out_be16(&ddata->base->swsrr, 0x556c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	out_be16(&ddata->base->swsrr, 0xaa39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	spin_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int mpc8xxx_wdt_start(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct mpc8xxx_wdt_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		container_of(w, struct mpc8xxx_wdt_ddata, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 tmp = in_be32(&ddata->base->swcrr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* Good, fire up the show */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	tmp &= ~(SWCRR_SWTC | SWCRR_SWF | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	tmp |= SWCRR_SWEN | SWCRR_SWPR | (ddata->swtc << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		tmp |= SWCRR_SWRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	out_be32(&ddata->base->swcrr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	tmp = in_be32(&ddata->base->swcrr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (!(tmp & SWCRR_SWEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	ddata->swtc = tmp >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	set_bit(WDOG_HW_RUNNING, &ddata->wdd.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int mpc8xxx_wdt_ping(struct watchdog_device *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct mpc8xxx_wdt_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		container_of(w, struct mpc8xxx_wdt_ddata, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mpc8xxx_wdt_keepalive(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct watchdog_info mpc8xxx_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.firmware_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.identity = "MPC8xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct watchdog_ops mpc8xxx_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.start = mpc8xxx_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.ping = mpc8xxx_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	const struct mpc8xxx_wdt_type *wdt_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct mpc8xxx_wdt_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 freq = fsl_get_sys_freq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	wdt_type = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (!wdt_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (!freq || freq == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ddata->base = devm_platform_ioremap_resource(ofdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (IS_ERR(ddata->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return PTR_ERR(ddata->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (!enabled && wdt_type->hw_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		dev_info(dev, "could not be enabled in software\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		bool status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		u32 __iomem *rsr = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (!rsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		status = in_be32(rsr) & wdt_type->rsr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		 /* clear reset status bits related to watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		out_be32(rsr, wdt_type->rsr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		iounmap(rsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_info(dev, "Last boot was %scaused by watchdog\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			 status ? "" : "not ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	spin_lock_init(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ddata->wdd.info = &mpc8xxx_wdt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ddata->wdd.ops = &mpc8xxx_wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ddata->wdd.timeout = WATCHDOG_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	watchdog_init_timeout(&ddata->wdd, timeout, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	watchdog_set_nowayout(&ddata->wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ddata->swtc = min(ddata->wdd.timeout * freq / wdt_type->prescaler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			  0xffffU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 * If the watchdog was previously enabled or we're running on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * MPC8xxx, we should ping the wdt from the kernel until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * userspace handles it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		mpc8xxx_wdt_start(&ddata->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ddata->wdd.max_hw_heartbeat_ms = (ddata->swtc * wdt_type->prescaler) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 					 (freq / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ddata->wdd.min_timeout = ddata->wdd.max_hw_heartbeat_ms / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (ddata->wdd.timeout < ddata->wdd.min_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ddata->wdd.timeout = ddata->wdd.min_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ret = devm_watchdog_register_device(dev, &ddata->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		 "WDT driver for MPC8xxx initialized. mode:%s timeout=%d sec\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		 reset ? "reset" : "interrupt", ddata->wdd.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	platform_set_drvdata(ofdev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct of_device_id mpc8xxx_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.compatible = "mpc83xx_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.data = &(struct mpc8xxx_wdt_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			.prescaler = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			.rsr_mask = BIT(3), /* RSR Bit SWRS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.compatible = "fsl,mpc8610-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.data = &(struct mpc8xxx_wdt_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			.prescaler = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			.hw_enabled = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			.rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.compatible = "fsl,mpc823-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.data = &(struct mpc8xxx_wdt_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			.prescaler = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			.hw_enabled = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			.rsr_mask = BIT(28), /* RSR Bit SWRS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct platform_driver mpc8xxx_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.probe		= mpc8xxx_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.name = "mpc8xxx_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.of_match_table = mpc8xxx_wdt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int __init mpc8xxx_wdt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return platform_driver_register(&mpc8xxx_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) arch_initcall(mpc8xxx_wdt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void __exit mpc8xxx_wdt_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	platform_driver_unregister(&mpc8xxx_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) module_exit(mpc8xxx_wdt_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		   "uProcessors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_LICENSE("GPL");