^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * MOXA ART SoCs watchdog driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Jonas Jensen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jonas Jensen <jonas.jensen@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_COUNT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_MODE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_ENABLE 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct moxart_wdt_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct watchdog_device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int clock_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int moxart_wdt_restart(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct moxart_wdt_dev *moxart_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) writel(1, moxart_wdt->base + REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) writel(0x5ab9, moxart_wdt->base + REG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) writel(0x03, moxart_wdt->base + REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int moxart_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct moxart_wdt_dev *moxart_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel(0, moxart_wdt->base + REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int moxart_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct moxart_wdt_dev *moxart_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel(moxart_wdt->clock_frequency * wdt_dev->timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) moxart_wdt->base + REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writel(0x5ab9, moxart_wdt->base + REG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(0x03, moxart_wdt->base + REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int moxart_wdt_set_timeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) wdt_dev->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct watchdog_info moxart_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .identity = "moxart-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct watchdog_ops moxart_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .start = moxart_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .stop = moxart_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .set_timeout = moxart_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .restart = moxart_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int moxart_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct moxart_wdt_dev *moxart_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int max_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) moxart_wdt = devm_kzalloc(dev, sizeof(*moxart_wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!moxart_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) platform_set_drvdata(pdev, moxart_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) moxart_wdt->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (IS_ERR(moxart_wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return PTR_ERR(moxart_wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pr_err("%s: of_clk_get failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) moxart_wdt->clock_frequency = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (moxart_wdt->clock_frequency == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pr_err("%s: incorrect clock frequency\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) max_timeout = UINT_MAX / moxart_wdt->clock_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) moxart_wdt->dev.info = &moxart_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) moxart_wdt->dev.ops = &moxart_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) moxart_wdt->dev.timeout = max_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) moxart_wdt->dev.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) moxart_wdt->dev.max_timeout = max_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) moxart_wdt->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) watchdog_init_timeout(&moxart_wdt->dev, heartbeat, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) watchdog_set_nowayout(&moxart_wdt->dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) watchdog_set_restart_priority(&moxart_wdt->dev, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) watchdog_set_drvdata(&moxart_wdt->dev, moxart_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) watchdog_stop_on_unregister(&moxart_wdt->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err = devm_watchdog_register_device(dev, &moxart_wdt->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_dbg(dev, "Watchdog enabled (heartbeat=%d sec, nowayout=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) moxart_wdt->dev.timeout, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct of_device_id moxart_watchdog_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .compatible = "moxa,moxart-watchdog" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_DEVICE_TABLE(of, moxart_watchdog_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct platform_driver moxart_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .probe = moxart_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "moxart-watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .of_match_table = moxart_watchdog_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) module_platform_driver(moxart_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_DESCRIPTION("MOXART watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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