Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Mellanox watchdog driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2019 Mellanox Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2019 Michael Shych <mshych@mellanox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_data/mlxreg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MLXREG_WDT_CLOCK_SCALE		1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MLXREG_WDT_MAX_TIMEOUT_TYPE1	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MLXREG_WDT_MAX_TIMEOUT_TYPE2	255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MLXREG_WDT_MAX_TIMEOUT_TYPE3	65535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MLXREG_WDT_MIN_TIMEOUT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MLXREG_WDT_OPTIONS_BASE (WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 				 WDIOF_SETTIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * struct mlxreg_wdt - wd private data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * @wdd:	watchdog device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @device:	basic device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @pdata:	data received from platform driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @regmap:	register map of parent device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @timeout:	defined timeout in sec.;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @action_idx:	index for direct access to action register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @timeout_idx:index for direct access to TO register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @tleft_idx:	index for direct access to time left register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @ping_idx:	index for direct access to ping register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @reset_idx:	index for direct access to reset cause register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @wd_type:	watchdog HW type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct mlxreg_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct mlxreg_core_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	void *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int action_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int timeout_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int tleft_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int ping_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int reset_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int regmap_val_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	enum mlxreg_wdt_type wdt_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void mlxreg_wdt_check_card_reset(struct mlxreg_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct mlxreg_core_data *reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (wdt->reset_idx == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (!(wdt->wdd.info->options & WDIOF_CARDRESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	reg_data = &wdt->pdata->data[wdt->reset_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		if (regval & ~reg_data->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			wdt->wdd.bootstatus = WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			dev_info(wdt->wdd.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				 "watchdog previously reset the CPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int mlxreg_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				  BIT(reg_data->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int mlxreg_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				  ~BIT(reg_data->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int mlxreg_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->ping_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return regmap_update_bits_base(wdt->regmap, reg_data->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				       ~reg_data->mask, BIT(reg_data->bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				       NULL, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int mlxreg_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				  unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->timeout_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 regval, set_time, hw_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	switch (wdt->wdt_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case MLX_WDT_TYPE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		hw_timeout = order_base_2(timeout * MLXREG_WDT_CLOCK_SCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		regval = (regval & reg_data->mask) | hw_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/* Rowndown to actual closest number of sec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		set_time = BIT(hw_timeout) / MLXREG_WDT_CLOCK_SCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		rc = regmap_write(wdt->regmap, reg_data->reg, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case MLX_WDT_TYPE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		set_time = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		rc = regmap_write(wdt->regmap, reg_data->reg, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case MLX_WDT_TYPE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		/* WD_TYPE3 has 2B set time register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		set_time = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (wdt->regmap_val_sz == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			regval = timeout & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			rc = regmap_write(wdt->regmap, reg_data->reg, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				regval = (timeout & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				rc = regmap_write(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 						reg_data->reg + 1, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			rc = regmap_write(wdt->regmap, reg_data->reg, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	wdd->timeout = set_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 * Restart watchdog with new timeout period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 * if watchdog is already started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (watchdog_active(wdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			rc = mlxreg_wdt_stop(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				rc = mlxreg_wdt_start(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static unsigned int mlxreg_wdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->tleft_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 regval, msb, lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (wdt->wdt_type == MLX_WDT_TYPE2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/* WD_TYPE3 has 2 byte timeleft register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (wdt->regmap_val_sz == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			rc = regmap_read(wdt->regmap, reg_data->reg, &lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				rc = regmap_read(wdt->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 						reg_data->reg + 1, &msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				regval = (msb & 0xff) << 8 | (lsb & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* Return 0 timeleft in case of failure register read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return rc == 0 ? regval : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct watchdog_ops mlxreg_wdt_ops_type1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.start		= mlxreg_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.stop		= mlxreg_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.ping		= mlxreg_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.set_timeout	= mlxreg_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct watchdog_ops mlxreg_wdt_ops_type2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.start		= mlxreg_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.stop		= mlxreg_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.ping		= mlxreg_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.set_timeout	= mlxreg_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.get_timeleft	= mlxreg_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct watchdog_info mlxreg_wdt_main_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.options	= MLXREG_WDT_OPTIONS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			| WDIOF_CARDRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.identity	= "mlx-wdt-main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct watchdog_info mlxreg_wdt_aux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.options	= MLXREG_WDT_OPTIONS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			| WDIOF_ALARMONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.identity	= "mlx-wdt-aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void mlxreg_wdt_config(struct mlxreg_wdt *wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			      struct mlxreg_core_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct mlxreg_core_data *data = pdata->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	wdt->reset_idx = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	for (i = 0; i < pdata->counter; i++, data++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		if (strnstr(data->label, "action", sizeof(data->label)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			wdt->action_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		else if (strnstr(data->label, "timeout", sizeof(data->label)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			wdt->timeout_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		else if (strnstr(data->label, "timeleft", sizeof(data->label)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			wdt->tleft_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		else if (strnstr(data->label, "ping", sizeof(data->label)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			wdt->ping_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		else if (strnstr(data->label, "reset", sizeof(data->label)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			wdt->reset_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	wdt->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (strnstr(pdata->identity, mlxreg_wdt_main_info.identity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		    sizeof(mlxreg_wdt_main_info.identity)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		wdt->wdd.info = &mlxreg_wdt_main_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		wdt->wdd.info = &mlxreg_wdt_aux_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	wdt->wdt_type = pdata->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	switch (wdt->wdt_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	case MLX_WDT_TYPE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		wdt->wdd.ops = &mlxreg_wdt_ops_type1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case MLX_WDT_TYPE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		wdt->wdd.ops = &mlxreg_wdt_ops_type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	case MLX_WDT_TYPE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		wdt->wdd.ops = &mlxreg_wdt_ops_type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	wdt->wdd.min_timeout = MLXREG_WDT_MIN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int mlxreg_wdt_init_timeout(struct mlxreg_wdt *wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				   struct mlxreg_core_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	timeout = pdata->data[wdt->timeout_idx].health_cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return mlxreg_wdt_set_timeout(&wdt->wdd, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int mlxreg_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct mlxreg_core_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct mlxreg_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		dev_err(dev, "Failed to get platform data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	wdt->wdd.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	wdt->regmap = pdata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	rc = regmap_get_val_bytes(wdt->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	wdt->regmap_val_sz = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	mlxreg_wdt_config(wdt, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if ((pdata->features & MLXREG_CORE_WD_FEATURE_NOWAYOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	watchdog_stop_on_reboot(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	watchdog_stop_on_unregister(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	watchdog_set_drvdata(&wdt->wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	rc = mlxreg_wdt_init_timeout(wdt, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		goto register_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if ((pdata->features & MLXREG_CORE_WD_FEATURE_START_AT_BOOT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		rc = mlxreg_wdt_start(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			goto register_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	mlxreg_wdt_check_card_reset(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	rc = devm_watchdog_register_device(dev, &wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) register_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		dev_err(dev, "Cannot register watchdog device (err=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct platform_driver mlxreg_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.probe	= mlxreg_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			.name = "mlx-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) module_platform_driver(mlxreg_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_AUTHOR("Michael Shych <michaelsh@mellanox.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_DESCRIPTION("Mellanox watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_ALIAS("platform:mlx-wdt");