Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DEFAULT_TIMEOUT	30	/* seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GXBB_WDT_CTRL_REG			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define GXBB_WDT_TCNT_REG			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define GXBB_WDT_RSET_REG			0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define GXBB_WDT_CTRL_CLKDIV_EN			BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GXBB_WDT_CTRL_CLK_EN			BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define GXBB_WDT_CTRL_EE_RESET			BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GXBB_WDT_CTRL_EN			BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GXBB_WDT_CTRL_DIV_MASK			(BIT(18) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GXBB_WDT_TCNT_SETUP_MASK		(BIT(16) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GXBB_WDT_TCNT_CNT_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct meson_gxbb_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct watchdog_device wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static int meson_gxbb_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	       data->reg_base + GXBB_WDT_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int meson_gxbb_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	       data->reg_base + GXBB_WDT_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static int meson_gxbb_wdt_ping(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	writel(0, data->reg_base + GXBB_WDT_RSET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int meson_gxbb_wdt_set_timeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				      unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned long tcnt = timeout * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (tcnt > GXBB_WDT_TCNT_SETUP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		tcnt = GXBB_WDT_TCNT_SETUP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	wdt_dev->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	meson_gxbb_wdt_ping(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static unsigned int meson_gxbb_wdt_get_timeleft(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return ((reg & GXBB_WDT_TCNT_SETUP_MASK) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		(reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static const struct watchdog_ops meson_gxbb_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.start = meson_gxbb_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.stop = meson_gxbb_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.ping = meson_gxbb_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.set_timeout = meson_gxbb_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.get_timeleft = meson_gxbb_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct watchdog_info meson_gxbb_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.identity = "Meson GXBB Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int __maybe_unused meson_gxbb_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (watchdog_active(&data->wdt_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		meson_gxbb_wdt_start(&data->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int __maybe_unused meson_gxbb_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct meson_gxbb_wdt *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (watchdog_active(&data->wdt_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		meson_gxbb_wdt_stop(&data->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct dev_pm_ops meson_gxbb_wdt_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	SET_SYSTEM_SLEEP_PM_OPS(meson_gxbb_wdt_suspend, meson_gxbb_wdt_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct of_device_id meson_gxbb_wdt_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 { .compatible = "amlogic,meson-gxbb-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_DEVICE_TABLE(of, meson_gxbb_wdt_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void meson_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int meson_gxbb_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct meson_gxbb_wdt *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	data->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (IS_ERR(data->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return PTR_ERR(data->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	data->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (IS_ERR(data->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return PTR_ERR(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = clk_prepare_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ret = devm_add_action_or_reset(dev, meson_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				       data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	data->wdt_dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	data->wdt_dev.info = &meson_gxbb_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	data->wdt_dev.ops = &meson_gxbb_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	data->wdt_dev.max_hw_heartbeat_ms = GXBB_WDT_TCNT_SETUP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	data->wdt_dev.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	data->wdt_dev.timeout = DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	watchdog_set_drvdata(&data->wdt_dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Setup with 1ms timebase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	writel(((clk_get_rate(data->clk) / 1000) & GXBB_WDT_CTRL_DIV_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		GXBB_WDT_CTRL_EE_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		GXBB_WDT_CTRL_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		GXBB_WDT_CTRL_CLKDIV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		data->reg_base + GXBB_WDT_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	meson_gxbb_wdt_set_timeout(&data->wdt_dev, data->wdt_dev.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	watchdog_stop_on_reboot(&data->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return devm_watchdog_register_device(dev, &data->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct platform_driver meson_gxbb_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.probe	= meson_gxbb_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.name = "meson-gxbb-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.pm = &meson_gxbb_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.of_match_table	= meson_gxbb_wdt_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) module_platform_driver(meson_gxbb_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MODULE_DESCRIPTION("Amlogic Meson GXBB Watchdog timer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_LICENSE("Dual BSD/GPL");