Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Maxim MAX77620 Watchdog Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct max77620_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct device			*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct regmap			*rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct watchdog_device		wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static int max77620_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 				  MAX77620_WDTEN, MAX77620_WDTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int max77620_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 				  MAX77620_WDTEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int max77620_wdt_ping(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				  MAX77620_WDTC_MASK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int max77620_wdt_set_timeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				    unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned int wdt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	switch (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case 0 ... 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		regval = MAX77620_TWD_2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		wdt_timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	case 3 ... 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		regval = MAX77620_TWD_16s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		wdt_timeout = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	case 17 ... 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		regval = MAX77620_TWD_64s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		wdt_timeout = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		regval = MAX77620_TWD_128s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		wdt_timeout = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				 MAX77620_WDTC_MASK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				 MAX77620_TWD_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	wdt_dev->timeout = wdt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static const struct watchdog_info max77620_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.identity = "max77620-watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct watchdog_ops max77620_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.start		= max77620_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.stop		= max77620_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.ping		= max77620_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.set_timeout	= max77620_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int max77620_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct max77620_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct watchdog_device *wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	wdt->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	wdt->rmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (!wdt->rmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		dev_err(wdt->dev, "Failed to get parent regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	wdt_dev = &wdt->wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	wdt_dev->info = &max77620_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	wdt_dev->ops = &max77620_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	wdt_dev->min_timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	wdt_dev->max_timeout = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	wdt_dev->max_hw_heartbeat_ms = 128 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	platform_set_drvdata(pdev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* Enable WD_RST_WK - WDT expire results in a restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ret = regmap_update_bits(wdt->rmap, MAX77620_REG_ONOFFCNFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				 MAX77620_ONOFFCNFG2_WD_RST_WK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				 MAX77620_ONOFFCNFG2_WD_RST_WK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		dev_err(wdt->dev, "Failed to set WD_RST_WK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* Set WDT clear in OFF and sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				 MAX77620_WDTOFFC | MAX77620_WDTSLPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				 MAX77620_WDTOFFC | MAX77620_WDTSLPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		dev_err(wdt->dev, "Failed to set WDT OFF mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Check if WDT running and if yes then set flags properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ret = regmap_read(wdt->rmap, MAX77620_REG_CNFGGLBL2, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		dev_err(wdt->dev, "Failed to read WDT CFG register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	switch (regval & MAX77620_TWD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	case MAX77620_TWD_2s:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		wdt_dev->timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case MAX77620_TWD_16s:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		wdt_dev->timeout = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	case MAX77620_TWD_64s:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		wdt_dev->timeout = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		wdt_dev->timeout = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (regval & MAX77620_WDTEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	watchdog_set_nowayout(wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	watchdog_set_drvdata(wdt_dev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	watchdog_stop_on_unregister(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return devm_watchdog_register_device(dev, wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct platform_device_id max77620_wdt_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ .name = "max77620-watchdog", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_DEVICE_TABLE(platform, max77620_wdt_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct platform_driver max77620_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.name	= "max77620-watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.probe	= max77620_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.id_table = max77620_wdt_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) module_platform_driver(max77620_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_DESCRIPTION("Max77620 watchdog timer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_LICENSE("GPL v2");