^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NXP LPC18xx Watchdog Timer (WDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * -----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * counter which decrements on every clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC18XX_WDT_MOD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPC18XX_WDT_MOD_WDEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPC18XX_WDT_MOD_WDRESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC18XX_WDT_TC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC18XX_WDT_TC_MIN 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPC18XX_WDT_TC_MAX 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC18XX_WDT_FEED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC18XX_WDT_FEED_MAGIC1 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC18XX_WDT_FEED_MAGIC2 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC18XX_WDT_TV 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Clock pre-scaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC18XX_WDT_CLK_DIV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Timeout values in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC18XX_WDT_DEF_TIMEOUT 30U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __MODULE_STRING(LPC18XX_WDT_DEF_TIMEOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct lpc18xx_wdt_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct watchdog_device wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *reg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *wdt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int lpc18xx_wdt_feed(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * An abort condition will occur if an interrupt happens during the feed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void lpc18xx_wdt_timer_feed(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct lpc18xx_wdt_dev *lpc18xx_wdt = from_timer(lpc18xx_wdt, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) lpc18xx_wdt_feed(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Use safe value (1/2 of real timeout) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mod_timer(&lpc18xx_wdt->timer, jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) msecs_to_jiffies((wdt_dev->timeout * MSEC_PER_SEC) / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Since LPC18xx Watchdog cannot be disabled in hardware, we must keep feeding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * it with a timer until userspace watchdog software takes over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int lpc18xx_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) lpc18xx_wdt_timer_feed(&lpc18xx_wdt->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev *lpc18xx_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) LPC18XX_WDT_CLK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int lpc18xx_wdt_set_timeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int new_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) lpc18xx_wdt->wdt_dev.timeout = new_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned int lpc18xx_wdt_get_timeleft(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int lpc18xx_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (timer_pending(&lpc18xx_wdt->timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) del_timer(&lpc18xx_wdt->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val |= LPC18XX_WDT_MOD_WDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val |= LPC18XX_WDT_MOD_WDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Setting the WDEN bit in the WDMOD register is not sufficient to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * enable the Watchdog. A valid feed sequence must be completed after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * setting WDEN before the Watchdog is capable of generating a reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) lpc18xx_wdt_feed(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int lpc18xx_wdt_restart(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Incorrect feed sequence causes immediate watchdog reset if enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= LPC18XX_WDT_MOD_WDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) val |= LPC18XX_WDT_MOD_WDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct watchdog_info lpc18xx_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .identity = "NXP LPC18xx Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .options = WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct watchdog_ops lpc18xx_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .start = lpc18xx_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .stop = lpc18xx_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .ping = lpc18xx_wdt_feed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .set_timeout = lpc18xx_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .get_timeleft = lpc18xx_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .restart = lpc18xx_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void lpc18xx_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int lpc18xx_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct lpc18xx_wdt_dev *lpc18xx_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) lpc18xx_wdt = devm_kzalloc(dev, sizeof(*lpc18xx_wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!lpc18xx_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) lpc18xx_wdt->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (IS_ERR(lpc18xx_wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return PTR_ERR(lpc18xx_wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) lpc18xx_wdt->reg_clk = devm_clk_get(dev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (IS_ERR(lpc18xx_wdt->reg_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "failed to get the reg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return PTR_ERR(lpc18xx_wdt->reg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) lpc18xx_wdt->wdt_clk = devm_clk_get(dev, "wdtclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(lpc18xx_wdt->wdt_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(dev, "failed to get the wdt clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return PTR_ERR(lpc18xx_wdt->wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = clk_prepare_enable(lpc18xx_wdt->reg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(dev, "could not prepare or enable sys clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) lpc18xx_wdt->reg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = clk_prepare_enable(lpc18xx_wdt->wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(dev, "could not prepare or enable wdt clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) lpc18xx_wdt->wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* We use the clock rate to calculate timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (lpc18xx_wdt->clk_rate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(dev, "failed to get clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) lpc18xx_wdt->wdt_dev.info = &lpc18xx_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) lpc18xx_wdt->wdt_dev.ops = &lpc18xx_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) lpc18xx_wdt->wdt_dev.min_timeout = DIV_ROUND_UP(LPC18XX_WDT_TC_MIN *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) lpc18xx_wdt->wdt_dev.max_timeout = (LPC18XX_WDT_TC_MAX *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) lpc18xx_wdt->wdt_dev.timeout = min(lpc18xx_wdt->wdt_dev.max_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LPC18XX_WDT_DEF_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) spin_lock_init(&lpc18xx_wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) lpc18xx_wdt->wdt_dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) watchdog_set_drvdata(&lpc18xx_wdt->wdt_dev, lpc18xx_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) watchdog_init_timeout(&lpc18xx_wdt->wdt_dev, heartbeat, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) timer_setup(&lpc18xx_wdt->timer, lpc18xx_wdt_timer_feed, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) watchdog_set_nowayout(&lpc18xx_wdt->wdt_dev, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) watchdog_set_restart_priority(&lpc18xx_wdt->wdt_dev, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) platform_set_drvdata(pdev, lpc18xx_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) watchdog_stop_on_reboot(&lpc18xx_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return devm_watchdog_register_device(dev, &lpc18xx_wdt->wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int lpc18xx_wdt_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_warn(&pdev->dev, "I quit now, hardware will probably reboot!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) del_timer_sync(&lpc18xx_wdt->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct of_device_id lpc18xx_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .compatible = "nxp,lpc1850-wwdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DEVICE_TABLE(of, lpc18xx_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct platform_driver lpc18xx_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "lpc18xx-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .of_match_table = lpc18xx_wdt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .probe = lpc18xx_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .remove = lpc18xx_wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) module_platform_driver(lpc18xx_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DESCRIPTION("NXP LPC18xx Watchdog Timer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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