Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Based on EP93xx wdt driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LTQ_XRX_RCU_RST_STAT		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LTQ_XRX_RCU_RST_STAT_WDT	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* CPU0 Reset Source Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LTQ_FALCON_SYS1_CPU0RS		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* reset cause mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LTQ_FALCON_SYS1_CPU0RS_MASK	0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LTQ_FALCON_SYS1_CPU0RS_WDT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * Section 3.4 of the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * The password sequence protects the WDT control register from unintended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * write actions, which might cause malfunction of the WDT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * essentially the following two magic passwords need to be written to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * IO access to the WDT core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LTQ_WDT_CR_PW1		0x00BE0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LTQ_WDT_CR_PW2		0x00DC0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define LTQ_WDT_CR		0x0		/* watchdog control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define  LTQ_WDT_CR_GEN		BIT(31)		/* enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Pre-warning limit set to 1/16 of max WDT period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define  LTQ_WDT_CR_PWL		(0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* set clock divider to 0x40000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define  LTQ_WDT_CR_CLKDIV	(0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define  LTQ_WDT_CR_PW_MASK	GENMASK(23, 16)	/* Password field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define  LTQ_WDT_CR_MAX_TIMEOUT	((1 << 16) - 1)	/* The reload field is 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LTQ_WDT_SR		0x8		/* watchdog status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define  LTQ_WDT_SR_EN		BIT(31)		/* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define  LTQ_WDT_SR_VALUE_MASK	GENMASK(15, 0)	/* Timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define LTQ_WDT_DIVIDER		0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct ltq_wdt_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	int (*bootstatus_get)(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct ltq_wdt_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct watchdog_device wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return __raw_readl(priv->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__raw_writel(val, priv->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			 u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 val = ltq_wdt_r32(priv, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	val &= ~(clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ltq_wdt_w32(priv, val, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return container_of(wdt, struct ltq_wdt_priv, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static struct watchdog_info ltq_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		   WDIOF_CARDRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.identity = "ltq_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int ltq_wdt_start(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	timeout = wdt->timeout * priv->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* write the second magic plus the configuration and new timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		     LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		     LTQ_WDT_CR_PW2 | timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		     LTQ_WDT_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int ltq_wdt_stop(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		     LTQ_WDT_CR_PW2, LTQ_WDT_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int ltq_wdt_ping(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	timeout = wdt->timeout * priv->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* write the second magic plus the configuration and new timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		     LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u64 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return do_div(timeout, priv->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct watchdog_ops ltq_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.start		= ltq_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.stop		= ltq_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.ping		= ltq_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.get_timeleft	= ltq_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct regmap *rcu_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (IS_ERR(rcu_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return PTR_ERR(rcu_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct regmap *rcu_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 						     "lantiq,rcu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (IS_ERR(rcu_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return PTR_ERR(rcu_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int ltq_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct ltq_wdt_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct watchdog_device *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	const struct ltq_wdt_hw *ltq_wdt_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	priv->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (IS_ERR(priv->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return PTR_ERR(priv->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* we do not need to enable the clock as it is always running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	clk = clk_get_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!priv->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		dev_err(dev, "clock rate less than divider %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			LTQ_WDT_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	wdt = &priv->wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	wdt->info		= &ltq_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	wdt->ops		= &ltq_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	wdt->min_timeout	= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	wdt->max_timeout	= LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	wdt->timeout		= wdt->max_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	wdt->parent		= dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ltq_wdt_hw = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		ret = ltq_wdt_hw->bootstatus_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			wdt->bootstatus = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	watchdog_set_nowayout(wdt, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	watchdog_init_timeout(wdt, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	status = ltq_wdt_r32(priv, LTQ_WDT_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (status & LTQ_WDT_SR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		 * If the watchdog is already running overwrite it with our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		 * new settings. Stop is not needed as the start call will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		 * replace all settings anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		ltq_wdt_start(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		set_bit(WDOG_HW_RUNNING, &wdt->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return devm_watchdog_register_device(dev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.bootstatus_get = ltq_wdt_xrx_bootstatus_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct ltq_wdt_hw ltq_wdt_falcon = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.bootstatus_get = ltq_wdt_falcon_bootstatus_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct of_device_id ltq_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	{ .compatible = "lantiq,wdt", .data = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	{ .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	{ .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DEVICE_TABLE(of, ltq_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct platform_driver ltq_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.probe = ltq_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.name = "wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.of_match_table = ltq_wdt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) module_platform_driver(ltq_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_AUTHOR("John Crispin <john@phrozen.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_DESCRIPTION("Lantiq SoC Watchdog");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_LICENSE("GPL");