^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * JZ4740 Watchdog driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/ingenic-tcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEFAULT_HEARTBEAT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_HEARTBEAT 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static unsigned int heartbeat = DEFAULT_HEARTBEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param(heartbeat, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "Watchdog heartbeat period in seconds from 1 to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __MODULE_STRING(MAX_HEARTBEAT) ", default "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __MODULE_STRING(DEFAULT_HEARTBEAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct jz4740_wdt_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct watchdog_device wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regmap_write(drvdata->map, TCU_REG_WDT_TCNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int new_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 timeout_value = (u16)(drvdata->clk_rate * new_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int tcer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regmap_read(drvdata->map, TCU_REG_WDT_TCER, &tcer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) regmap_write(drvdata->map, TCU_REG_WDT_TCER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) regmap_write(drvdata->map, TCU_REG_WDT_TDR, timeout_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_write(drvdata->map, TCU_REG_WDT_TCNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (tcer & TCU_WDT_TCER_TCEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_write(drvdata->map, TCU_REG_WDT_TCER, TCU_WDT_TCER_TCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) wdt_dev->timeout = new_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int tcer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = clk_prepare_enable(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regmap_read(drvdata->map, TCU_REG_WDT_TCER, &tcer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Start watchdog if it wasn't started already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!(tcer & TCU_WDT_TCER_TCEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_write(drvdata->map, TCU_REG_WDT_TCER, TCU_WDT_TCER_TCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regmap_write(drvdata->map, TCU_REG_WDT_TCER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk_disable_unprepare(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int jz4740_wdt_restart(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) wdt_dev->timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) jz4740_wdt_start(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct watchdog_info jz4740_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .identity = "jz4740 Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct watchdog_ops jz4740_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .start = jz4740_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .stop = jz4740_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .ping = jz4740_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .set_timeout = jz4740_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .restart = jz4740_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct of_device_id jz4740_wdt_of_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .compatible = "ingenic,jz4740-watchdog", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .compatible = "ingenic,jz4780-watchdog", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MODULE_DEVICE_TABLE(of, jz4740_wdt_of_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int jz4740_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct jz4740_wdt_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct watchdog_device *jz4740_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) drvdata = devm_kzalloc(dev, sizeof(struct jz4740_wdt_drvdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) drvdata->clk = devm_clk_get(&pdev->dev, "wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (IS_ERR(drvdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(&pdev->dev, "cannot find WDT clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return PTR_ERR(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Set smallest clock possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rate = clk_round_rate(drvdata->clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = clk_set_rate(drvdata->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) drvdata->clk_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) jz4740_wdt = &drvdata->wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) jz4740_wdt->info = &jz4740_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) jz4740_wdt->ops = &jz4740_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) jz4740_wdt->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) jz4740_wdt->max_timeout = 0xffff / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) jz4740_wdt->timeout = clamp(heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) jz4740_wdt->min_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) jz4740_wdt->max_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) jz4740_wdt->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) watchdog_set_nowayout(jz4740_wdt, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) watchdog_set_drvdata(jz4740_wdt, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) drvdata->map = device_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (IS_ERR(drvdata->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(dev, "regmap not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return PTR_ERR(drvdata->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return devm_watchdog_register_device(dev, &drvdata->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct platform_driver jz4740_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .probe = jz4740_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = "jz4740-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .of_match_table = of_match_ptr(jz4740_wdt_of_matches),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) module_platform_driver(jz4740_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_DESCRIPTION("jz4740 Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_ALIAS("platform:jz4740-wdt");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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