^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Watchdog Timer Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for ITE IT87xx Environment Control - Low Pin Count Input / Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (c) Copyright 2007 Oliver Schuster <olivers137@aol.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on softdog.c by Alan Cox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 83977f_wdt.c by Jose Goncalves,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it87.c by Chris Gauthron, Jean Delvare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Data-sheets: Publicly available at the ITE website
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * http://www.ite.com.tw/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Support of the watchdog timers, which are available on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IT8607, IT8620, IT8622, IT8625, IT8628, IT8655, IT8665, IT8686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726, IT8728,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * IT8772, IT8783 and IT8784.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WATCHDOG_NAME "IT87 WDT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Defaults for Module Parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DEFAULT_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DEFAULT_TESTMODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DEFAULT_NOWAYOUT WATCHDOG_NOWAYOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* IO Ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VAL 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Logical device Numbers LDN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Configuration Registers and Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LDNREG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHIPID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CHIPREV 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Chip Id numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NO_DEV_ID 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IT8607_ID 0x8607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IT8620_ID 0x8620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IT8622_ID 0x8622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IT8625_ID 0x8625
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IT8628_ID 0x8628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IT8655_ID 0x8655
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IT8665_ID 0x8665
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IT8686_ID 0x8686
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IT8702_ID 0x8702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IT8705_ID 0x8705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IT8712_ID 0x8712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IT8716_ID 0x8716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IT8718_ID 0x8718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IT8720_ID 0x8720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IT8721_ID 0x8721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IT8726_ID 0x8726 /* the data sheet suggest wrongly 0x8716 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IT8728_ID 0x8728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IT8772_ID 0x8772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IT8783_ID 0x8783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IT8784_ID 0x8784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IT8786_ID 0x8786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* GPIO Configuration Registers LDN=0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WDTCTRL 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WDTCFG 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WDTVALLSB 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WDTVALMSB 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* GPIO Bits WDTCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WDT_TOV1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WDT_KRST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WDT_TOVE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WDT_PWROK 0x10 /* not in it8721 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WDT_INT_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static unsigned int max_units, chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static unsigned int timeout = DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int testmode = DEFAULT_TESTMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static bool nowayout = DEFAULT_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) module_param(timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __MODULE_STRING(DEFAULT_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) module_param(testmode, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MODULE_PARM_DESC(testmode, "Watchdog test mode (1 = no reboot), default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __MODULE_STRING(DEFAULT_TESTMODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started, default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __MODULE_STRING(WATCHDOG_NOWAYOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Superio Chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline int superio_enter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Try to reserve REG and REG + 1 for exclusive access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!request_muxed_region(REG, 2, WATCHDOG_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) outb(0x87, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) outb(0x01, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) outb(0x55, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) outb(0x55, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void superio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) outb(0x02, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) outb(0x02, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) release_region(REG, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void superio_select(int ldn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) outb(LDNREG, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) outb(ldn, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline int superio_inb(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return inb(VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline void superio_outb(int val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) outb(val, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline int superio_inw(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) outb(reg++, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val = inb(VAL) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val |= inb(VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline void superio_outw(int val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) outb(reg++, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) outb(val >> 8, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) outb(val, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Internal function, should be called after superio_select(GPIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void _wdt_update_timeout(unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned char cfg = WDT_KRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (testmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (t <= max_units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cfg |= WDT_TOV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) t /= 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (chip_type != IT8721_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cfg |= WDT_PWROK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) superio_outb(cfg, WDTCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) superio_outb(t, WDTVALLSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (max_units > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) superio_outb(t >> 8, WDTVALMSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int wdt_update_timeout(unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) superio_select(GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) _wdt_update_timeout(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int wdt_round_time(int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) t += 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) t -= t % 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* watchdog timer handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return wdt_update_timeout(wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return wdt_update_timeout(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * wdt_set_timeout - set a new timeout value with watchdog ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @t: timeout value in seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * The hardware device has a 8 or 16 bit watchdog timer (depends on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * chip version) that can be configured to count seconds or minutes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Used within WDIOC_SETTIMEOUT watchdog device ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int wdt_set_timeout(struct watchdog_device *wdd, unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (t > max_units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) t = wdt_round_time(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) wdd->timeout = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (watchdog_hw_running(wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = wdt_update_timeout(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct watchdog_info ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .firmware_version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .identity = WATCHDOG_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct watchdog_ops wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .start = wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .stop = wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .set_timeout = wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct watchdog_device wdt_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .info = &ident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ops = &wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .min_timeout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int __init it87_wdt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 chip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) rc = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) chip_type = superio_inw(CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) chip_rev = superio_inb(CHIPREV) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case IT8702_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) max_units = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case IT8712_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) max_units = (chip_rev < 8) ? 255 : 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case IT8716_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case IT8726_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) max_units = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case IT8607_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case IT8620_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case IT8622_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case IT8625_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case IT8628_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case IT8655_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case IT8665_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case IT8686_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case IT8718_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case IT8720_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case IT8721_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case IT8728_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case IT8772_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case IT8783_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case IT8784_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case IT8786_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) max_units = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case IT8705_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pr_err("Unsupported Chip found, Chip %04x Revision %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) chip_type, chip_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case NO_DEV_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pr_err("no device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_err("Unknown Chip found, Chip %04x Revision %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) chip_type, chip_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) rc = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) superio_select(GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) superio_outb(WDT_TOV1, WDTCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) superio_outb(0x00, WDTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (timeout < 1 || timeout > max_units * 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) timeout = DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pr_warn("Timeout value out of range, use default %d sec\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DEFAULT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (timeout > max_units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) timeout = wdt_round_time(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) wdt_dev.timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) wdt_dev.max_timeout = max_units * 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) watchdog_stop_on_reboot(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) rc = watchdog_register_device(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_err("Cannot register watchdog device (err=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pr_info("Chip IT%04x revision %d initialized. timeout=%d sec (nowayout=%d testmode=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) chip_type, chip_rev, timeout, nowayout, testmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void __exit it87_wdt_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) watchdog_unregister_device(&wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) module_init(it87_wdt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) module_exit(it87_wdt_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_AUTHOR("Oliver Schuster");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_DESCRIPTION("Hardware Watchdog Device Driver for IT87xx EC-LPC I/O");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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