Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *      Intel_SCU 0.2:  An Intel SCU IOH Based Watchdog Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *			for Intel part #(s):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *				- AF82MP20 PCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *      Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __INTEL_SCU_WATCHDOG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __INTEL_SCU_WATCHDOG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define WDT_VER "0.3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* minimum time between interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MIN_TIME_CYCLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Time from warning to reboot is 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DEFAULT_SOFT_TO_HARD_MARGIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX_TIME 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEFAULT_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Ajustment to clock tick frequency to make timing come out right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FREQ_ADJUSTMENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct intel_scu_watchdog_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	ulong driver_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	ulong driver_closed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	u32 timer_started;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	u32 timer_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u32 soft_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u32 __iomem *timer_load_count_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u32 __iomem *timer_current_value_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u32 __iomem *timer_control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u32 __iomem *timer_clear_interrupt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u32 __iomem *timer_interrupt_status_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	struct sfi_timer_table_entry *timer_tbl_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	struct notifier_block intel_scu_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct miscdevice miscdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern int sfi_mtimer_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* __INTEL_SCU_WATCHDOG_H */