^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define WDOG_CS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define WDOG_CS_CMD32EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WDOG_CS_ULK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WDOG_CS_RCS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPO_CLK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPO_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WDOG_CS_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WDOG_CS_UPDATE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WDOG_CS_WAIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WDOG_CS_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WDOG_CNT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WDOG_TOVAL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REFRESH_SEQ0 0xA602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REFRESH_SEQ1 0xB480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UNLOCK_SEQ0 0xC520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UNLOCK_SEQ1 0xD928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UNLOCK ((UNLOCK_SEQ1 << 16) | UNLOCK_SEQ0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DEFAULT_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX_TIMEOUT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WDOG_CLOCK_RATE 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WDOG_WAIT_TIMEOUT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) module_param(nowayout, bool, 0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct imx7ulp_wdt_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int imx7ulp_wdt_wait(void __iomem *base, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 val = readl(base + WDOG_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!(val & mask) && readl_poll_timeout_atomic(base + WDOG_CS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val & mask, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) WDOG_WAIT_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 val = readl(wdt->base + WDOG_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(UNLOCK, wdt->base + WDOG_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) goto enable_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel(val | WDOG_CS_EN, wdt->base + WDOG_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enable_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static bool imx7ulp_wdt_is_enabled(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 val = readl(base + WDOG_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return val & WDOG_CS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int imx7ulp_wdt_ping(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel(REFRESH, wdt->base + WDOG_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int imx7ulp_wdt_start(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return imx7ulp_wdt_enable(wdog, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int imx7ulp_wdt_stop(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return imx7ulp_wdt_enable(wdog, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 val = WDOG_CLOCK_RATE * timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(UNLOCK, wdt->base + WDOG_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto timeout_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(val, wdt->base + WDOG_TOVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) wdog->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) timeout_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int imx7ulp_wdt_restart(struct watchdog_device *wdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = imx7ulp_wdt_enable(wdog, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = imx7ulp_wdt_set_timeout(&wdt->wdd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* wait for wdog to fire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) while (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct watchdog_ops imx7ulp_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .start = imx7ulp_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .stop = imx7ulp_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .ping = imx7ulp_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .set_timeout = imx7ulp_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .restart = imx7ulp_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct watchdog_info imx7ulp_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .identity = "i.MX7ULP watchdog timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int imx7ulp_wdt_init(void __iomem *base, unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* unlock the wdog for reconfiguration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = imx7ulp_wdt_wait(base, WDOG_CS_ULK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto init_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* set an initial timeout value in TOVAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(timeout, base + WDOG_TOVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* enable 32bit command sequence and reconfigure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) WDOG_CS_WAIT | WDOG_CS_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel(val, base + WDOG_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) imx7ulp_wdt_wait(base, WDOG_CS_RCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) init_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void imx7ulp_wdt_action(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int imx7ulp_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct imx7ulp_wdt_device *imx7ulp_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct watchdog_device *wdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!imx7ulp_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) platform_set_drvdata(pdev, imx7ulp_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (IS_ERR(imx7ulp_wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return PTR_ERR(imx7ulp_wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) imx7ulp_wdt->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(imx7ulp_wdt->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(dev, "Failed to get watchdog clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return PTR_ERR(imx7ulp_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = clk_prepare_enable(imx7ulp_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = devm_add_action_or_reset(dev, imx7ulp_wdt_action, imx7ulp_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) wdog = &imx7ulp_wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) wdog->info = &imx7ulp_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) wdog->ops = &imx7ulp_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) wdog->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) wdog->max_timeout = MAX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) wdog->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) wdog->timeout = DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) watchdog_init_timeout(wdog, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) watchdog_stop_on_reboot(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) watchdog_stop_on_unregister(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) watchdog_set_drvdata(wdog, imx7ulp_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return devm_watchdog_register_device(dev, wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (watchdog_active(&imx7ulp_wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk_disable_unprepare(imx7ulp_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int __maybe_unused imx7ulp_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = clk_prepare_enable(imx7ulp_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) imx7ulp_wdt_init(imx7ulp_wdt->base, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (watchdog_active(&imx7ulp_wdt->wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops, imx7ulp_wdt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) imx7ulp_wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { .compatible = "fsl,imx7ulp-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static struct platform_driver imx7ulp_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .probe = imx7ulp_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = "imx7ulp-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .pm = &imx7ulp_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .of_match_table = imx7ulp_wdt_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) module_platform_driver(imx7ulp_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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