^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) Copyright 2004 Google Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (c) Copyright 2005 David Härdeman <david@2gen.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on i810-tco.c which is in turn based on softdog.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The timer is implemented in the following I/O controller hubs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (See the intel documentation on http://developer.intel.com.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 6300ESB chip : document number 300641-004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 2004YYZZ Ross Biro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Initial version 0.01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 2004YYZZ Ross Biro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Version 0.02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 20050210 David Härdeman <david@2gen.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Ported driver to kernel 2.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 20171016 Radu Rendec <rrendec@arista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Change driver to use the watchdog subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Add support for multiple 6300ESB devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Includes, defines, variables, module parameters, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Module and version information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ESB_MODULE_NAME "i6300ESB timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PCI configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ESB_CONFIG_REG 0x60 /* Config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ESB_LOCK_REG 0x68 /* WDT lock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Memory mapped registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Lock register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Config register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Reload register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Magic constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ESB_HEARTBEAT_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ESB_HEARTBEAT_MAX 2046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ESB_HEARTBEAT_DEFAULT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ESB_HEARTBEAT_RANGE __MODULE_STRING(ESB_HEARTBEAT_MIN) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "<heartbeat<" __MODULE_STRING(ESB_HEARTBEAT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int heartbeat; /* in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_PARM_DESC(heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "Watchdog heartbeat in seconds. (" ESB_HEARTBEAT_RANGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ", default=" __MODULE_STRING(ESB_HEARTBEAT_DEFAULT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* internal variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct esb_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Some i6300ESB specific functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Prepare for reloading the timer by unlocking the proper registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * This is performed by first writing 0x80 followed by 0x86 to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * reload register. After this the appropriate registers can be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * to once before they need to be unlocked again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline void esb_unlock_registers(struct esb_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writew(ESB_UNLOCK1, ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writew(ESB_UNLOCK2, ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int esb_timer_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct esb_dev *edev = to_esb_dev(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int _wdd_nowayout = test_bit(WDOG_NO_WAY_OUT, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Enable or Enable + Lock? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = ESB_WDT_ENABLE | (_wdd_nowayout ? ESB_WDT_LOCK : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int esb_timer_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct esb_dev *edev = to_esb_dev(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* First, reset timers as suggested by the docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Then disable the WDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Returns 0 if the timer was disabled, non-zero otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return val & ESB_WDT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int esb_timer_keepalive(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct esb_dev *edev = to_esb_dev(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* FIXME: Do we need to flush anything here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int esb_timer_set_heartbeat(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct esb_dev *edev = to_esb_dev(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* We shift by 9, so if we are passed a value of 1 sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * val will be 1 << 9 = 512, then write that to two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val = time << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Write timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel(val, ESB_TIMER1_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Write timer 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(val, ESB_TIMER2_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* FIXME: Do we need to flush everything out? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) wdd->timeout = time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Watchdog Subsystem Interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct watchdog_info esb_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .identity = ESB_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct watchdog_ops esb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .start = esb_timer_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .stop = esb_timer_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .set_timeout = esb_timer_set_heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .ping = esb_timer_keepalive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Data for PCI driver interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct pci_device_id esb_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0, }, /* End of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Init & exit routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static unsigned char esb_getdevice(struct esb_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (pci_enable_device(edev->pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(&edev->pdev->dev, "failed to enable device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) goto err_devput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (pci_request_region(edev->pdev, 0, ESB_MODULE_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(&edev->pdev->dev, "failed to request region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) edev->base = pci_ioremap_bar(edev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (edev->base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Something's wrong here, BASEADDR has to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(&edev->pdev->dev, "failed to get BASEADDR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_set_drvdata(&edev->pdev->dev, edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) err_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pci_release_region(edev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pci_disable_device(edev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) err_devput:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void esb_initdevice(struct esb_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Config register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Bit 5 : 0 = Enable WDT_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Bit 2 : 0 = set the timer frequency to the PCI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * divided by 2^15 (approx 1KHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * The watchdog has two timers, it can be setup so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * expiry of timer1 results in an interrupt and the expiry of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * timer2 results in a reboot. We set it to not generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * any interrupts as there is not much we can do with it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * right now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pci_write_config_word(edev->pdev, ESB_CONFIG_REG, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Check that the WDT isn't already locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (val1 & ESB_WDT_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_warn(&edev->pdev->dev, "nowayout already set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Set the timer to watchdog mode and disable it for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Check if the watchdog was previously triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val2 = readw(ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (val2 & ESB_WDT_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) edev->wdd.bootstatus = WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Reset WDT_TIMEOUT flag and timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) esb_unlock_registers(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG(edev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* And set the correct timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) esb_timer_set_heartbeat(&edev->wdd, edev->wdd.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int esb_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct esb_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) edev = devm_kzalloc(&pdev->dev, sizeof(*edev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Check whether or not the hardware watchdog is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) edev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!esb_getdevice(edev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Initialize the watchdog and make sure it does not run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) edev->wdd.info = &esb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) edev->wdd.ops = &esb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) edev->wdd.min_timeout = ESB_HEARTBEAT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) edev->wdd.max_timeout = ESB_HEARTBEAT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) edev->wdd.timeout = ESB_HEARTBEAT_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) watchdog_init_timeout(&edev->wdd, heartbeat, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) watchdog_set_nowayout(&edev->wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) watchdog_stop_on_reboot(&edev->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) watchdog_stop_on_unregister(&edev->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) esb_initdevice(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Register the watchdog so that userspace has access to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = watchdog_register_device(&edev->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "initialized. heartbeat=%d sec (nowayout=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) edev->wdd.timeout, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) iounmap(edev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pci_release_region(edev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pci_disable_device(edev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void esb_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct esb_dev *edev = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) watchdog_unregister_device(&edev->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iounmap(edev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pci_release_region(edev->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pci_disable_device(edev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct pci_driver esb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .name = ESB_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .id_table = esb_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .probe = esb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .remove = esb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) module_pci_driver(esb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MODULE_AUTHOR("Ross Biro and David Härdeman");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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