^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2010-2011 Picochip Ltd., Jamie Iles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * https://www.picochip.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file implements a driver for the Synopsys DesignWare watchdog device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * in the many subsystems. The watchdog has 16 different timeout periods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and these are a function of the input clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The DesignWare watchdog cannot be stopped once it has been started so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * do not implement a stop function. The watchdog core will continue to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * heartbeat requests after the watchdog device has been closed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/limits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WDOG_CONTROL_REG_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WDOG_INTERRUPT_STATUS_REG_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WDOG_INTERRUPT_CLEAR_REG_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WDOG_COMP_PARAMS_5_REG_OFFSET 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WDOG_COMP_PARAMS_4_REG_OFFSET 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WDOG_COMP_PARAMS_3_REG_OFFSET 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WDOG_COMP_PARAMS_2_REG_OFFSET 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WDOG_COMP_PARAMS_1_REG_OFFSET 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WDOG_COMP_PARAMS_1_USE_FIX_TOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WDOG_COMP_VERSION_REG_OFFSET 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WDOG_COMP_TYPE_REG_OFFSET 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DW_WDT_NUM_TOPS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DW_WDT_FIX_TOP(_idx) (1U << (16 + _idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DW_WDT_DEFAULT_SECONDS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const u32 dw_wdt_fix_tops[DW_WDT_NUM_TOPS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DW_WDT_FIX_TOP(0), DW_WDT_FIX_TOP(1), DW_WDT_FIX_TOP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DW_WDT_FIX_TOP(3), DW_WDT_FIX_TOP(4), DW_WDT_FIX_TOP(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DW_WDT_FIX_TOP(6), DW_WDT_FIX_TOP(7), DW_WDT_FIX_TOP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DW_WDT_FIX_TOP(9), DW_WDT_FIX_TOP(10), DW_WDT_FIX_TOP(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DW_WDT_FIX_TOP(12), DW_WDT_FIX_TOP(13), DW_WDT_FIX_TOP(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DW_WDT_FIX_TOP(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum dw_wdt_rmod {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DW_WDT_RMOD_RESET = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DW_WDT_RMOD_IRQ = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct dw_wdt_timeout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 top_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct dw_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum dw_wdt_rmod rmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct dw_wdt_timeout timeouts[DW_WDT_NUM_TOPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Save/restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct dentry *dbgfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) WDOG_CONTROL_REG_WDT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (rmod == DW_WDT_RMOD_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dw_wdt->rmod = rmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int timeout, u32 *top_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Find a TOP with timeout greater or equal to the requested number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Note we'll select a TOP with maximum timeout if the requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * timeout couldn't be reached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (dw_wdt->timeouts[idx].sec >= timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (idx == DW_WDT_NUM_TOPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) --idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *top_val = dw_wdt->timeouts[idx].top_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return dw_wdt->timeouts[idx].sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * We'll find a timeout greater or equal to one second anyway because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * the driver probe would have failed if there was none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (dw_wdt->timeouts[idx].sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return dw_wdt->timeouts[idx].sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u64 msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return msec < UINT_MAX ? msec : UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (dw_wdt->timeouts[idx].top_val == top_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * In IRQ mode due to the two stages counter, the actual timeout is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * twice greater than the TOP setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int dw_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) WDOG_COUNTER_RESTART_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 top_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Note IRQ mode being enabled means having a non-zero pre-timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * setup. In this case we try to find a TOP as close to the half of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * requested timeout as possible since DW Watchdog IRQ mode is designed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * in two stages way - first timeout rises the pre-timeout interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * second timeout performs the system reset. So basically the effective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * watchdog-caused reset happens after two watchdog TOPs elapsed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &top_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) wdd->pretimeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) wdd->pretimeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Set the new value in the watchdog. Some versions of dw_wdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * have have TOPINIT in the TIMEOUT_RANGE register (as per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * effectively get a pat of the watchdog right here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Kick new TOP value into the watchdog counter if activated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (watchdog_active(wdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dw_wdt_ping(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * In case users set bigger timeout value than HW can support,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * kernel(watchdog_dev.c) helps to feed watchdog before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * wdd->max_hw_heartbeat_ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) wdd->timeout = timeout * dw_wdt->rmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) wdd->timeout = top_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int dw_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * We ignore actual value of the timeout passed from user-space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * using it as a flag whether the pretimeout functionality is intended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * to be activated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dw_wdt_set_timeout(wdd, wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Disable/enable interrupt mode depending on the RMOD flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Enable watchdog. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val |= WDOG_CONTROL_REG_WDT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int dw_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dw_wdt_set_timeout(wdd, wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dw_wdt_ping(&dw_wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dw_wdt_arm_system_reset(dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int dw_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!dw_wdt->rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) set_bit(WDOG_HW_RUNNING, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reset_control_assert(dw_wdt->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reset_control_deassert(dw_wdt->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int dw_wdt_restart(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (dw_wdt_is_enabled(dw_wdt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel(WDOG_COUNTER_RESTART_KICK_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dw_wdt_arm_system_reset(dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* wait for reset to assert... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mdelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sec = val / dw_wdt->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) sec += wdd->pretimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct watchdog_info dw_wdt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .identity = "Synopsys DesignWare Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct watchdog_info dw_wdt_pt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) WDIOF_PRETIMEOUT | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .identity = "Synopsys DesignWare Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct watchdog_ops dw_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .start = dw_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .stop = dw_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .ping = dw_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .set_timeout = dw_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .set_pretimeout = dw_wdt_set_pretimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .get_timeleft = dw_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .restart = dw_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static irqreturn_t dw_wdt_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct dw_wdt *dw_wdt = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * We don't clear the IRQ status. It's supposed to be done by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * following ping operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) watchdog_notify_pretimeout(&dw_wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int dw_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk_disable_unprepare(dw_wdt->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) clk_disable_unprepare(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int dw_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int err = clk_prepare_enable(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err = clk_prepare_enable(dw_wdt->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk_disable_unprepare(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dw_wdt_ping(&dw_wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * In case if DW WDT IP core is synthesized with fixed TOP feature disabled the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * TOPs array can be arbitrary ordered with nearly any sixteen uint numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * depending on the system engineer imagination. The next method handles the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * passed TOPs array to pre-calculate the effective timeouts and to sort the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * TOP items out in the ascending order with respect to the timeouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct dw_wdt_timeout tout, *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int val, tidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u64 msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * We walk over the passed TOPs array and calculate corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * timeouts in seconds and milliseconds. The milliseconds granularity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * is needed to distinguish the TOPs with very close timeouts and to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * set the watchdog max heartbeat setting further.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (val = 0; val < DW_WDT_NUM_TOPS; ++val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) tout.top_val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tout.sec = tops[val] / dw_wdt->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) msec = (u64)tops[val] * MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) do_div(msec, dw_wdt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Find a suitable place for the current TOP in the timeouts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * array so that the list is remained in the ascending order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (tidx = 0; tidx < val; ++tidx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dst = &dw_wdt->timeouts[tidx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (tout.sec > dst->sec || (tout.sec == dst->sec &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tout.msec >= dst->msec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) swap(*dst, tout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dw_wdt->timeouts[val] = tout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 data, of_tops[DW_WDT_NUM_TOPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) const u32 *tops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Retrieve custom or fixed counter values depending on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * WDT_USE_FIX_TOP flag found in the component specific parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * #1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (data & WDOG_COMP_PARAMS_1_USE_FIX_TOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) tops = dw_wdt_fix_tops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = of_property_read_variable_u32_array(dev_of_node(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DW_WDT_NUM_TOPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_warn(dev, "No valid TOPs array specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tops = dw_wdt_fix_tops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tops = of_tops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Convert the specified TOPs into an array of watchdog timeouts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dw_wdt_handle_tops(dw_wdt, tops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(dev, "No any valid TOP detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DW_WDT_DBGFS_REG(_name, _off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .offset = _off \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct debugfs_reg32 dw_wdt_dbgfs_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DW_WDT_DBGFS_REG("cr", WDOG_CONTROL_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DW_WDT_DBGFS_REG("torr", WDOG_TIMEOUT_RANGE_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DW_WDT_DBGFS_REG("ccvr", WDOG_CURRENT_COUNT_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DW_WDT_DBGFS_REG("crr", WDOG_COUNTER_RESTART_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DW_WDT_DBGFS_REG("stat", WDOG_INTERRUPT_STATUS_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DW_WDT_DBGFS_REG("param5", WDOG_COMP_PARAMS_5_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DW_WDT_DBGFS_REG("param4", WDOG_COMP_PARAMS_4_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DW_WDT_DBGFS_REG("param3", WDOG_COMP_PARAMS_3_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DW_WDT_DBGFS_REG("param2", WDOG_COMP_PARAMS_2_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DW_WDT_DBGFS_REG("param1", WDOG_COMP_PARAMS_1_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DW_WDT_DBGFS_REG("version", WDOG_COMP_VERSION_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DW_WDT_DBGFS_REG("type", WDOG_COMP_TYPE_REG_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct device *dev = dw_wdt->wdd.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct debugfs_regset32 *regset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!regset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) regset->regs = dw_wdt_dbgfs_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) regset->base = dw_wdt->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) debugfs_remove_recursive(dw_wdt->dbgfs_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #else /* !CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #endif /* !CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int dw_wdt_drv_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct dw_wdt *dw_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!dw_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (IS_ERR(dw_wdt->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return PTR_ERR(dw_wdt->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Try to request the watchdog dedicated timer clock source. It must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * be supplied if asynchronous mode is enabled. Otherwise fallback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * to the common timer/bus clocks configuration, in which the very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * first found clock supply both timer and APB signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dw_wdt->clk = devm_clk_get(dev, "tclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (IS_ERR(dw_wdt->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dw_wdt->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (IS_ERR(dw_wdt->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return PTR_ERR(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = clk_prepare_enable(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dw_wdt->rate = clk_get_rate(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (dw_wdt->rate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Request APB clock if device is configured with async clocks mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * In this case both tclk and pclk clocks are supposed to be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Alas we can't know for sure whether async mode was really activated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * so the pclk phandle reference is left optional. If it couldn't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * found we consider the device configured in synchronous clocks mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dw_wdt->pclk = devm_clk_get_optional(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (IS_ERR(dw_wdt->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = PTR_ERR(dw_wdt->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = clk_prepare_enable(dw_wdt->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (IS_ERR(dw_wdt->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = PTR_ERR(dw_wdt->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto out_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Enable normal reset without pre-timeout by default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Pre-timeout IRQ is optional, since some hardware may lack support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * of it. Note we must request rising-edge IRQ, since the lane is left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * pending either until the next watchdog kick event or up to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * system reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = devm_request_irq(dev, ret, dw_wdt_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) IRQF_SHARED | IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pdev->name, dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto out_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dw_wdt->wdd.info = &dw_wdt_pt_ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto out_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dw_wdt->wdd.info = &dw_wdt_ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) reset_control_deassert(dw_wdt->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ret = dw_wdt_init_timeouts(dw_wdt, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) wdd = &dw_wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) wdd->ops = &dw_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) watchdog_set_drvdata(wdd, dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) watchdog_set_nowayout(wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) watchdog_init_timeout(wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * If the watchdog is already running, use its already configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * timeout. Otherwise use the default or the value provided through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * devicetree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (dw_wdt_is_enabled(dw_wdt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) wdd->timeout = dw_wdt_get_timeout(dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) set_bit(WDOG_HW_RUNNING, &wdd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) wdd->timeout = DW_WDT_DEFAULT_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) watchdog_init_timeout(wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) platform_set_drvdata(pdev, dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) watchdog_set_restart_priority(wdd, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = watchdog_register_device(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto out_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dw_wdt_dbgfs_init(dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) out_disable_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) clk_disable_unprepare(dw_wdt->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) out_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) clk_disable_unprepare(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int dw_wdt_drv_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dw_wdt_dbgfs_clear(dw_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) watchdog_unregister_device(&dw_wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) reset_control_assert(dw_wdt->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) clk_disable_unprepare(dw_wdt->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) clk_disable_unprepare(dw_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const struct of_device_id dw_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { .compatible = "snps,dw-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static struct platform_driver dw_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .probe = dw_wdt_drv_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .remove = dw_wdt_drv_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .name = "dw_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .of_match_table = of_match_ptr(dw_wdt_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .pm = &dw_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) module_platform_driver(dw_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MODULE_AUTHOR("Jamie Iles");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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