^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/char/watchdog/davinci_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Watchdog driver for DaVinci DM644x/DM646x processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006-2013 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 2007 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MODULE_NAME "DAVINCI-WDT: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DEFAULT_HEARTBEAT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Timer register set definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PID12 (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EMUMGT (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIM12 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TIM34 (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRD12 (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PRD34 (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TCR (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TGCR (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WDTCR (0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* TCR bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ENAMODE12_DISABLED (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ENAMODE12_ONESHOT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ENAMODE12_PERIODIC (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* TGCR bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TIM12RS_UNRESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TIM34RS_UNRESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TIMMODE_64BIT_WDOG (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* WDTCR bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WDEN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WDFLAG (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WDKEY_SEQ0 (0xa5c6 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WDKEY_SEQ1 (0xda7e << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * struct to hold data for each WDT device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @base - base io address of WD device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @clk - source clock of WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @wdd - hold watchdog device as is in WDT core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct davinci_wdt_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct watchdog_device wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int davinci_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 tgcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 timer_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long wdt_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) wdt_freq = clk_get_rate(davinci_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* disable, internal clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) iowrite32(0, davinci_wdt->base + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* reset timer, set mode to 64-bit watchdog, and unreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) iowrite32(0, davinci_wdt->base + TGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) iowrite32(tgcr, davinci_wdt->base + TGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* clear counter regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) iowrite32(0, davinci_wdt->base + TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) iowrite32(0, davinci_wdt->base + TIM34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* set timeout period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) iowrite32(timer_margin, davinci_wdt->base + PRD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) iowrite32(timer_margin, davinci_wdt->base + PRD34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* enable run continuously */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Once the WDT is in pre-active state write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * write protected (except for the WDKEY field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* put watchdog in pre-active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* put watchdog in active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int davinci_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* put watchdog in service state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* put watchdog in active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u64 timer_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* if timeout has occured then return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = ioread32(davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (val & WDFLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) freq = clk_get_rate(davinci_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) timer_counter = ioread32(davinci_wdt->base + TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) do_div(timer_counter, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return wdd->timeout - timer_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int davinci_wdt_restart(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 tgcr, wdtcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* disable, internal clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) iowrite32(0, davinci_wdt->base + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* reset timer, set mode to 64-bit watchdog, and unreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tgcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) iowrite32(tgcr, davinci_wdt->base + TGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) iowrite32(tgcr, davinci_wdt->base + TGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* clear counter and period regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) iowrite32(0, davinci_wdt->base + TIM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) iowrite32(0, davinci_wdt->base + TIM34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) iowrite32(0, davinci_wdt->base + PRD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) iowrite32(0, davinci_wdt->base + PRD34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* put watchdog in pre-active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) wdtcr = WDKEY_SEQ0 | WDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) iowrite32(wdtcr, davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* put watchdog in active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) wdtcr = WDKEY_SEQ1 | WDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) iowrite32(wdtcr, davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* write an invalid value to the WDKEY field to trigger a restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) wdtcr = 0x00004000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) iowrite32(wdtcr, davinci_wdt->base + WDTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct watchdog_info davinci_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .options = WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .identity = "DaVinci/Keystone Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct watchdog_ops davinci_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .start = davinci_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .stop = davinci_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .ping = davinci_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .get_timeleft = davinci_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .restart = davinci_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void davinci_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int davinci_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct watchdog_device *wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct davinci_wdt_device *davinci_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!davinci_wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) davinci_wdt->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (IS_ERR(davinci_wdt->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return dev_err_probe(dev, PTR_ERR(davinci_wdt->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "failed to get clock node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = clk_prepare_enable(davinci_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(dev, "failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = devm_add_action_or_reset(dev, davinci_clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) davinci_wdt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) platform_set_drvdata(pdev, davinci_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) wdd = &davinci_wdt->wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) wdd->info = &davinci_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) wdd->ops = &davinci_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) wdd->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) wdd->max_timeout = MAX_HEARTBEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) wdd->timeout = DEFAULT_HEARTBEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) wdd->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) watchdog_init_timeout(wdd, heartbeat, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) watchdog_set_drvdata(wdd, davinci_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) watchdog_set_nowayout(wdd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) watchdog_set_restart_priority(wdd, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (IS_ERR(davinci_wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return PTR_ERR(davinci_wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return devm_watchdog_register_device(dev, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct of_device_id davinci_wdt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .compatible = "ti,davinci-wdt", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct platform_driver platform_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "davinci-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .of_match_table = davinci_wdt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .probe = davinci_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) module_platform_driver(platform_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_AUTHOR("Texas Instruments");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_DESCRIPTION("DaVinci Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) module_param(heartbeat, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_PARM_DESC(heartbeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "Watchdog heartbeat period in seconds from 1 to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __MODULE_STRING(MAX_HEARTBEAT) ", default "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __MODULE_STRING(DEFAULT_HEARTBEAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_ALIAS("platform:davinci-wdt");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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