Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * coh901327_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008-2009 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DRV_NAME "WDOG COH 901 327"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * COH 901 327 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* WDOG_FEED Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define U300_WDOG_FR							0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define U300_WDOG_FR_FEED_RESTART_TIMER					0xFEEDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* WDOG_TIMEOUT Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define U300_WDOG_TR							0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define U300_WDOG_TR_TIMEOUT_MASK					0x7FFFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* WDOG_DISABLE1 Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define U300_WDOG_D1R							0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define U300_WDOG_D1R_DISABLE1_DISABLE_TIMER				0x2BADU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* WDOG_DISABLE2 Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define U300_WDOG_D2R							0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define U300_WDOG_D2R_DISABLE2_DISABLE_TIMER				0xCAFEU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define U300_WDOG_D2R_DISABLE_STATUS_DISABLED				0xDABEU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define U300_WDOG_D2R_DISABLE_STATUS_ENABLED				0x0000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* WDOG_STATUS Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define U300_WDOG_SR							0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define U300_WDOG_SR_STATUS_TIMED_OUT					0xCFE8U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define U300_WDOG_SR_STATUS_NORMAL					0x0000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define U300_WDOG_SR_RESET_STATUS_RESET					0xE8B4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* WDOG_COUNT Register 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define U300_WDOG_CR							0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define U300_WDOG_CR_VALID_IND						0x8000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define U300_WDOG_CR_VALID_STABLE					0x0000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define U300_WDOG_CR_COUNT_VALUE_MASK					0x7FFFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* WDOG_JTAGOVR Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define U300_WDOG_JOR							0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define U300_WDOG_JOR_JTAG_MODE_IND					0x0002U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE				0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* WDOG_RESTART Register 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define U300_WDOG_RR							0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define U300_WDOG_RR_RESTART_VALUE_RESUME				0xACEDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* WDOG_IRQ_EVENT Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define U300_WDOG_IER							0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND				0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE				0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* WDOG_IRQ_MASK Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define U300_WDOG_IMR							0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE				0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* WDOG_IRQ_FORCE Register 32bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define U300_WDOG_IFR							0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE			0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Default timeout in seconds = 1 minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define U300_WDOG_DEFAULT_TIMEOUT					60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static unsigned int margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * Enabling and disabling functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static void coh901327_enable(u16 timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned long delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Restart timer if it is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	val = readw(virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		       virtbase + U300_WDOG_RR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* Acknowledge any pending interrupt so it doesn't just fire off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	       virtbase + U300_WDOG_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * The interrupt is cleared in the 32 kHz clock domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * Wait 3 32 kHz cycles for it to take effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	delay_ns = DIV_ROUND_UP(1000000000, freq); /* Freq to ns and round up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	delay_ns = 3 * delay_ns; /* Wait 3 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ndelay(delay_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* Enable the watchdog interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Activate the watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	writew(timeout, virtbase + U300_WDOG_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Start the watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	writew(U300_WDOG_FR_FEED_RESTART_TIMER, virtbase + U300_WDOG_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * Extra read so that this change propagate in the watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	(void) readw(virtbase + U300_WDOG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	val = readw(virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		dev_err(parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			"%s(): watchdog not enabled! D2R value %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			__func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void coh901327_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* Disable the watchdog interrupt if it is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	writew(0x0000U, virtbase + U300_WDOG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* If the watchdog is currently enabled, attempt to disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	val = readw(virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		writew(U300_WDOG_D1R_DISABLE1_DISABLE_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		       virtbase + U300_WDOG_D1R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		       virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* Write this twice (else problems occur) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		       virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	val = readw(virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		dev_err(parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			"%s(): watchdog not disabled! D2R value %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			__func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int coh901327_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	coh901327_enable(wdt_dev->timeout * 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int coh901327_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	coh901327_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int coh901327_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* Feed the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	writew(U300_WDOG_FR_FEED_RESTART_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	       virtbase + U300_WDOG_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int coh901327_settimeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				unsigned int time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	wdt_dev->timeout = time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Set new timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	writew(time * 100, virtbase + U300_WDOG_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* Feed the dog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	writew(U300_WDOG_FR_FEED_RESTART_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	       virtbase + U300_WDOG_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* Read repeatedly until the value is stable! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	val = readw(virtbase + U300_WDOG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	while (val & U300_WDOG_CR_VALID_IND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		val = readw(virtbase + U300_WDOG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	val &= U300_WDOG_CR_COUNT_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		val /= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * This interrupt occurs 10 ms before the watchdog WILL bark.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static irqreturn_t coh901327_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * Ack IRQ? If this occurs we're FUBAR anyway, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * just acknowledge, disable the interrupt and await the imminent end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * If you at some point need a host of callbacks to be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * when the system is about to watchdog-reset, add them here!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * NOTE: on future versions of this IP-block, it will be possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 * to prevent a watchdog reset by feeding the watchdog at this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	val = readw(virtbase + U300_WDOG_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		       virtbase + U300_WDOG_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	writew(0x0000U, virtbase + U300_WDOG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	dev_crit(parent, "watchdog is barking!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct watchdog_info coh901327_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.identity = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct watchdog_ops coh901327_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.start = coh901327_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.stop = coh901327_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.ping = coh901327_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.set_timeout = coh901327_settimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.get_timeleft = coh901327_gettimeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct watchdog_device coh901327_wdt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.info = &coh901327_ident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.ops = &coh901327_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * Max timeout is 327 since the 10ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * timeout register is max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * 0x7FFF = 327670ms ~= 327s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.min_timeout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.max_timeout = 327,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.timeout = U300_WDOG_DEFAULT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int __init coh901327_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	virtbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (IS_ERR(virtbase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return PTR_ERR(virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	clk = clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		dev_err(dev, "could not get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		dev_err(dev, "could not prepare and enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		goto out_no_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	val = readw(virtbase + U300_WDOG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case U300_WDOG_SR_STATUS_TIMED_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev_info(dev, "watchdog timed out since last chip reset!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		/* Status will be cleared below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	case U300_WDOG_SR_STATUS_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		dev_info(dev, "in normal status, no timeouts have occurred.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dev_info(dev, "contains an illegal status code (%08x)\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	val = readw(virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	case U300_WDOG_D2R_DISABLE_STATUS_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		dev_info(dev, "currently disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	case U300_WDOG_D2R_DISABLE_STATUS_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		dev_info(dev, "currently enabled! (disabling it now)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		coh901327_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		dev_err(dev, "contains an illegal enable/disable code (%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* Reset the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (request_irq(irq, coh901327_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			DRV_NAME " Bark", pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		goto out_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	watchdog_init_timeout(&coh901327_wdt, margin, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	coh901327_wdt.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	ret = watchdog_register_device(&coh901327_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		goto out_no_wdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	dev_info(dev, "initialized. (timeout=%d sec)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			coh901327_wdt.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) out_no_wdog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	free_irq(irq, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) out_no_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) out_no_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static u16 wdogenablestore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static u16 irqmaskstore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int coh901327_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	irqmaskstore = readw(virtbase + U300_WDOG_IMR) & 0x0001U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	wdogenablestore = readw(virtbase + U300_WDOG_D2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/* If watchdog is on, disable it here and now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		coh901327_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int coh901327_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/* Restore the watchdog interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	writew(irqmaskstore, virtbase + U300_WDOG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		/* Restart the watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		       virtbase + U300_WDOG_RR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		writew(U300_WDOG_FR_FEED_RESTART_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		       virtbase + U300_WDOG_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define coh901327_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define coh901327_resume  NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  * Mistreating the watchdog is the only way to perform a software reset of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * system on EMP platforms. So we implement this and export a symbol for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void coh901327_watchdog_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	/* Enable even if on JTAG too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	writew(U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	       virtbase + U300_WDOG_JOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 * Timeout = 5s, we have to wait for the watchdog reset to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	 * actually take place: the watchdog will be reloaded with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	 * default value immediately, so we HAVE to reboot and get back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	 * into the kernel in 30s, or the device will reboot again!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	 * The boot loader will typically deactivate the watchdog, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 * need time enough for the boot loader to get to the point of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 * deactivating the watchdog before it is shut down by it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	 * NOTE: on future versions of the watchdog, this restriction is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	 * gone: the watchdog will be reloaded with a default value (1 min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	 * instead of last value, and you can conveniently set the watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	 * timeout to 10ms (value = 1) without any problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	coh901327_enable(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	/* Return and await doom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct of_device_id coh901327_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	{ .compatible = "stericsson,coh901327" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct platform_driver coh901327_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		.name	= "coh901327_wdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		.of_match_table = coh901327_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.suspend	= coh901327_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.resume		= coh901327_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) builtin_platform_driver_probe(coh901327_driver, coh901327_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* not really modular, but ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) module_param(margin, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");