Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (C) 2018 ROHM Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // ROHM BD70528MWV watchdog driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/mfd/rohm-bd70528.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Max time we can set is 1 hour, 59 minutes and 59 seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * and Minimum time is 1 second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define WDT_MAX_MS	((2 * 60 * 60 - 1) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define WDT_MIN_MS	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DEFAULT_TIMEOUT	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define WD_CTRL_MAGIC1 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define WD_CTRL_MAGIC2 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct wdtbd70528 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct rohm_regmap_dev *mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct watchdog_device wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * bd70528_wdt_set - arm or disarm watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @data:	device data for the PMIC instance we want to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @enable:	new state of WDT. zero to disable, non zero to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @old_state:	previous state of WDT will be filled here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Arm or disarm WDT on BD70528 PMIC. Expected to be called only by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * BD70528 RTC and BD70528 WDT drivers. The rtc_timer_lock must be taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * by calling bd70528_wdt_lock before calling bd70528_wdt_set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct bd70528_data *bd70528 = container_of(data, struct bd70528_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 						 chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8 wd_ctrl_arr[3] = { WD_CTRL_MAGIC1, WD_CTRL_MAGIC2, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8 *wd_ctrl = &wd_ctrl_arr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	ret = regmap_read(bd70528->chip.regmap, BD70528_REG_WDT_CTRL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	*wd_ctrl = (u8)tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (old_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		if (*wd_ctrl & BD70528_MASK_WDT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			*old_state |= BD70528_WDT_STATE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			*old_state &= ~BD70528_WDT_STATE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		if ((!enable) == (!(*old_state & BD70528_WDT_STATE_BIT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		if (*wd_ctrl & BD70528_MASK_WDT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		*wd_ctrl |= BD70528_MASK_WDT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		if (*wd_ctrl & BD70528_MASK_WDT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			*wd_ctrl &= ~BD70528_MASK_WDT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		ret = regmap_write(bd70528->chip.regmap, BD70528_REG_WDT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				   wd_ctrl_arr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ret = regmap_read(bd70528->chip.regmap, BD70528_REG_WDT_CTRL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if ((tmp & BD70528_MASK_WDT_EN) != (*wd_ctrl & BD70528_MASK_WDT_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		dev_err(bd70528->chip.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			"Watchdog ctrl mismatch (hw) 0x%x (set) 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			tmp, *wd_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) EXPORT_SYMBOL(bd70528_wdt_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * bd70528_wdt_lock - take WDT lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @data:	device data for the PMIC instance we want to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * Lock WDT for arming/disarming in order to avoid race condition caused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * by WDT state changes initiated by WDT and RTC drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void bd70528_wdt_lock(struct rohm_regmap_dev *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct bd70528_data *bd70528 = container_of(data, struct bd70528_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 						 chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mutex_lock(&bd70528->rtc_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) EXPORT_SYMBOL(bd70528_wdt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * bd70528_wdt_unlock - unlock WDT lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * @data:	device data for the PMIC instance we want to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * Unlock WDT lock which has previously been taken by call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * bd70528_wdt_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct bd70528_data *bd70528 = container_of(data, struct bd70528_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 						 chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	mutex_unlock(&bd70528->rtc_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) EXPORT_SYMBOL(bd70528_wdt_unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int bd70528_wdt_set_locked(struct wdtbd70528 *w, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return bd70528_wdt_set(w->mfd, enable, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int bd70528_wdt_change(struct wdtbd70528 *w, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	bd70528_wdt_lock(w->mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ret = bd70528_wdt_set_locked(w, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	bd70528_wdt_unlock(w->mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int bd70528_wdt_start(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct wdtbd70528 *w = watchdog_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	dev_dbg(w->dev, "WDT ping...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return bd70528_wdt_change(w, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int bd70528_wdt_stop(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct wdtbd70528 *w = watchdog_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	dev_dbg(w->dev, "WDT stopping...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return bd70528_wdt_change(w, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int bd70528_wdt_set_timeout(struct watchdog_device *wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				   unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned int hours;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int minutes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int seconds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct wdtbd70528 *w = watchdog_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	seconds = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	hours = timeout / (60 * 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Maximum timeout is 1h 59m 59s => hours is 1 or 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (hours)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		seconds -= (60 * 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	minutes = seconds / 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	seconds = seconds % 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	bd70528_wdt_lock(w->mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ret = bd70528_wdt_set_locked(w, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ret = regmap_update_bits(w->regmap, BD70528_REG_WDT_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				 BD70528_MASK_WDT_HOUR, hours);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		dev_err(w->dev, "Failed to set WDT hours\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		goto out_en_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ret = regmap_update_bits(w->regmap, BD70528_REG_WDT_MINUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				 BD70528_MASK_WDT_MINUTE, bin2bcd(minutes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		dev_err(w->dev, "Failed to set WDT minutes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		goto out_en_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = regmap_update_bits(w->regmap, BD70528_REG_WDT_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				 BD70528_MASK_WDT_SEC, bin2bcd(seconds));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dev_err(w->dev, "Failed to set WDT seconds\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_dbg(w->dev, "WDT tmo set to %u\n", timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) out_en_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ret = bd70528_wdt_set_locked(w, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	bd70528_wdt_unlock(w->mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct watchdog_info bd70528_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.identity = "bd70528-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct watchdog_ops bd70528_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.start		= bd70528_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.stop		= bd70528_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.set_timeout	= bd70528_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int bd70528_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct rohm_regmap_dev *bd70528;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct wdtbd70528 *w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	bd70528 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (!bd70528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		dev_err(&pdev->dev, "No MFD driver data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	w = devm_kzalloc(&pdev->dev, sizeof(*w), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (!w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	w->regmap = bd70528->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	w->mfd = bd70528;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	w->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	w->wdt.info = &bd70528_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	w->wdt.ops =  &bd70528_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	w->wdt.min_hw_heartbeat_ms = WDT_MIN_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	w->wdt.max_hw_heartbeat_ms = WDT_MAX_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	w->wdt.parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	w->wdt.timeout = DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	watchdog_set_drvdata(&w->wdt, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	watchdog_init_timeout(&w->wdt, 0, pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = bd70528_wdt_set_timeout(&w->wdt, w->wdt.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		dev_err(&pdev->dev, "Failed to set the watchdog timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	bd70528_wdt_lock(w->mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	ret = regmap_read(w->regmap, BD70528_REG_WDT_CTRL, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	bd70528_wdt_unlock(w->mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_err(&pdev->dev, "Failed to get the watchdog state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (reg & BD70528_MASK_WDT_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		dev_dbg(&pdev->dev, "watchdog was running during probe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		set_bit(WDOG_HW_RUNNING, &w->wdt.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ret = devm_watchdog_register_device(&pdev->dev, &w->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		dev_err(&pdev->dev, "watchdog registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct platform_driver bd70528_wdt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.name = "bd70528-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.probe = bd70528_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) module_platform_driver(bd70528_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DESCRIPTION("BD70528 watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_ALIAS("platform:bd70528-wdt");