Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Watchdog driver for Broadcom BCM2835
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * "bcm2708_wdog" driver written by Luke Diamand that was obtained from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * branch "rpi-3.6.y" of git://github.com/raspberrypi/linux.git was used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * as a hardware reference for the Broadcom BCM2835 watchdog timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/bcm2835-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PM_RSTC				0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PM_RSTS				0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PM_WDOG				0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PM_PASSWORD			0x5a000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PM_WDOG_TIME_SET		0x000fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PM_RSTC_WRCFG_CLR		0xffffffcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PM_RSTS_HADWRH_SET		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PM_RSTC_WRCFG_SET		0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PM_RSTC_WRCFG_FULL_RESET	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PM_RSTC_RESET			0x00000102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * The Raspberry Pi firmware uses the RSTS register to know which partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Partition 63 is a special partition used by the firmware to indicate halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PM_RSTS_RASPBERRYPI_HALT	0x555
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SECS_TO_WDOG_TICKS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct bcm2835_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct bcm2835_wdt *bcm2835_power_off_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static unsigned int heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static bool bcm2835_wdt_is_running(struct bcm2835_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	uint32_t cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	cur = readl(wdt->base + PM_RSTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return !!(cur & PM_RSTC_WRCFG_FULL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int bcm2835_wdt_start(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	uint32_t cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	spin_lock_irqsave(&wdt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				PM_WDOG_TIME_SET), wdt->base + PM_WDOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	cur = readl_relaxed(wdt->base + PM_RSTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		  PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	spin_unlock_irqrestore(&wdt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int bcm2835_wdt_stop(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static unsigned int bcm2835_wdt_get_timeleft(struct watchdog_device *wdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	uint32_t ret = readl_relaxed(wdt->base + PM_WDOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void __bcm2835_restart(struct bcm2835_wdt *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* use a timeout of 10 ticks (~150us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	val = readl_relaxed(wdt->base + PM_RSTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	val &= PM_RSTC_WRCFG_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	writel_relaxed(val, wdt->base + PM_RSTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* No sleeping, possibly atomic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int bcm2835_restart(struct watchdog_device *wdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			   unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	__bcm2835_restart(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct watchdog_ops bcm2835_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.owner =	THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.start =	bcm2835_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.stop =		bcm2835_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.get_timeleft =	bcm2835_wdt_get_timeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.restart =	bcm2835_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct watchdog_info bcm2835_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.options =	WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			WDIOF_KEEPALIVEPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.identity =	"Broadcom BCM2835 Watchdog timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct watchdog_device bcm2835_wdt_wdd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.info =		&bcm2835_wdt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.ops =		&bcm2835_wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.min_timeout =	1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.max_timeout =	WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.timeout =	WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * We can't really power off, but if we do the normal reset scheme, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * indicate to bootcode.bin not to reboot, then most of the chip will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * powered off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void bcm2835_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct bcm2835_wdt *wdt = bcm2835_power_off_wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * We set the watchdog hard reset bit here to distinguish this reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * from the normal (full) reset. bootcode.bin will not reboot after a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * hard reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	val = readl_relaxed(wdt->base + PM_RSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	writel_relaxed(val, wdt->base + PM_RSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Continue with normal reset mechanism */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	__bcm2835_restart(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int bcm2835_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct bcm2835_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	wdt = devm_kzalloc(dev, sizeof(struct bcm2835_wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	spin_lock_init(&wdt->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	wdt->base = pm->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	watchdog_set_drvdata(&bcm2835_wdt_wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	watchdog_init_timeout(&bcm2835_wdt_wdd, heartbeat, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	watchdog_set_nowayout(&bcm2835_wdt_wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	bcm2835_wdt_wdd.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (bcm2835_wdt_is_running(wdt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		 * The currently active timeout value (set by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		 * bootloader) may be different from the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 * heartbeat parameter or the value in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		 * tree. But we just need to set WDOG_HW_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		 * because then the framework will "immediately" ping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		 * the device, updating the timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		set_bit(WDOG_HW_RUNNING, &bcm2835_wdt_wdd.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	watchdog_set_restart_priority(&bcm2835_wdt_wdd, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	watchdog_stop_on_reboot(&bcm2835_wdt_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	err = devm_watchdog_register_device(dev, &bcm2835_wdt_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (pm_power_off == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		pm_power_off = bcm2835_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		bcm2835_power_off_wdt = wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	dev_info(dev, "Broadcom BCM2835 watchdog timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int bcm2835_wdt_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (pm_power_off == bcm2835_power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		pm_power_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct platform_driver bcm2835_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.probe		= bcm2835_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.remove		= bcm2835_wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.name =		"bcm2835-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) module_platform_driver(bcm2835_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) module_param(heartbeat, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_ALIAS("platform:bcm2835-wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_DESCRIPTION("Driver for Broadcom BCM2835 watchdog timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_LICENSE("GPL");