Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Watchdog driver for CSR Atlas7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ATLAS7_TIMER_WDT_INDEX		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define ATLAS7_WDT_DEFAULT_TIMEOUT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define ATLAS7_WDT_CNT_CTRL	(0 + 4 * ATLAS7_TIMER_WDT_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define ATLAS7_WDT_CNT_MATCH	(0x18 + 4 * ATLAS7_TIMER_WDT_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ATLAS7_WDT_CNT		(0x48 +  4 * ATLAS7_TIMER_WDT_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ATLAS7_WDT_CNT_EN	(BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ATLAS7_WDT_EN		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static unsigned int timeout = ATLAS7_WDT_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) module_param(timeout, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct atlas7_wdog {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned long tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static unsigned int atlas7_wdt_gettimeleft(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 counter, match, delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	counter = readl(wdt->base + ATLAS7_WDT_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	match = readl(wdt->base + ATLAS7_WDT_CNT_MATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	delta = match - counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return  delta / wdt->tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int atlas7_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 counter, match, delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	counter = readl(wdt->base + ATLAS7_WDT_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	delta = wdd->timeout * wdt->tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	match = counter + delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	writel(match, wdt->base + ATLAS7_WDT_CNT_MATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int atlas7_wdt_enable(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	atlas7_wdt_ping(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) | ATLAS7_WDT_CNT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	      wdt->base + ATLAS7_WDT_CNT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writel(1, wdt->base + ATLAS7_WDT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int atlas7_wdt_disable(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel(0, wdt->base + ATLAS7_WDT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) & ~ATLAS7_WDT_CNT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	      wdt->base + ATLAS7_WDT_CNT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int atlas7_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	wdd->timeout = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct watchdog_info atlas7_wdt_ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.options = OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.firmware_version = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.identity = "atlas7 Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct watchdog_ops atlas7_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.start = atlas7_wdt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.stop = atlas7_wdt_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.get_timeleft = atlas7_wdt_gettimeleft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.ping = atlas7_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.set_timeout = atlas7_wdt_settimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct watchdog_device atlas7_wdd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.info = &atlas7_wdt_ident,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.ops = &atlas7_wdt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.timeout = ATLAS7_WDT_DEFAULT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct of_device_id atlas7_wdt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ .compatible = "sirf,atlas7-tick"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void atlas7_clk_disable_unprepare(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int atlas7_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct atlas7_wdog *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	wdt->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (IS_ERR(wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return PTR_ERR(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		dev_err(dev, "clk enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ret = devm_add_action_or_reset(dev, atlas7_clk_disable_unprepare, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* disable watchdog hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	writel(0, wdt->base + ATLAS7_WDT_CNT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	wdt->tick_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (!wdt->tick_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	wdt->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	atlas7_wdd.min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	atlas7_wdd.max_timeout = UINT_MAX / wdt->tick_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	watchdog_init_timeout(&atlas7_wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	watchdog_set_nowayout(&atlas7_wdd, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	watchdog_set_drvdata(&atlas7_wdd, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	platform_set_drvdata(pdev, &atlas7_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	watchdog_stop_on_reboot(&atlas7_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	watchdog_stop_on_unregister(&atlas7_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return devm_watchdog_register_device(dev, &atlas7_wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int __maybe_unused atlas7_wdt_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 * NOTE:timer controller registers settings are saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * and restored back by the timer-atlas7.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __maybe_unused atlas7_wdt_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct watchdog_device *wdd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * NOTE: Since timer controller registers settings are saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * and restored back by the timer-atlas7.c, so we need not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * update WD settings except refreshing timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	atlas7_wdt_ping(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static SIMPLE_DEV_PM_OPS(atlas7_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		atlas7_wdt_suspend, atlas7_wdt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_DEVICE_TABLE(of, atlas7_wdt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct platform_driver atlas7_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.name = "atlas7-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.pm = &atlas7_wdt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.of_match_table	= atlas7_wdt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.probe = atlas7_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) module_platform_driver(atlas7_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MODULE_DESCRIPTION("CSRatlas7 watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_AUTHOR("Guo Zeng <Guo.Zeng@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_ALIAS("platform:atlas7-wdt");